2012-07-04 18:43:33 +08:00
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/*
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* IMX31 UARTS
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*
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* Copyright (c) 2008 OKL
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* Originally Written by Hans Jiang
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* Copyright (c) 2011 NICTA Pty Ltd.
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2015-08-13 18:26:19 +08:00
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* Updated by Jean-Christophe Dubois <jcd@tribudubois.net>
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2012-07-04 18:43:33 +08:00
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*
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* This work is licensed under the terms of the GNU GPL, version 2 or later.
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* See the COPYING file in the top-level directory.
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*
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* This is a `bare-bones' implementation of the IMX series serial ports.
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* TODO:
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* -- implement FIFOs. The real hardware has 32 word transmit
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* and receive FIFOs; we currently use a 1-char buffer
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* -- implement DMA
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* -- implement BAUD-rate and modem lines, for when the backend
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* is a real serial device.
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*/
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2016-01-27 02:17:05 +08:00
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#include "qemu/osdep.h"
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2015-08-13 18:26:19 +08:00
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#include "hw/char/imx_serial.h"
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2019-08-12 13:23:42 +08:00
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#include "hw/irq.h"
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2019-08-12 13:23:51 +08:00
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#include "hw/qdev-properties.h"
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2020-12-12 06:05:12 +08:00
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#include "hw/qdev-properties-system.h"
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2019-08-12 13:23:45 +08:00
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#include "migration/vmstate.h"
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2015-12-15 20:16:16 +08:00
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#include "qemu/log.h"
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2019-05-23 22:35:07 +08:00
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#include "qemu/module.h"
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2012-07-04 18:43:33 +08:00
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2015-10-25 22:16:06 +08:00
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#ifndef DEBUG_IMX_UART
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#define DEBUG_IMX_UART 0
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2012-07-04 18:43:33 +08:00
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#endif
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2015-10-25 22:16:06 +08:00
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#define DPRINTF(fmt, args...) \
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do { \
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if (DEBUG_IMX_UART) { \
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fprintf(stderr, "[%s]%s: " fmt , TYPE_IMX_SERIAL, \
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__func__, ##args); \
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} \
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} while (0)
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2012-07-04 18:43:33 +08:00
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static const VMStateDescription vmstate_imx_serial = {
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2015-08-13 18:26:19 +08:00
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.name = TYPE_IMX_SERIAL,
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2018-03-16 03:11:41 +08:00
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.version_id = 2,
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.minimum_version_id = 2,
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2012-07-04 18:43:33 +08:00
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.fields = (VMStateField[]) {
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VMSTATE_INT32(readbuff, IMXSerialState),
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VMSTATE_UINT32(usr1, IMXSerialState),
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VMSTATE_UINT32(usr2, IMXSerialState),
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VMSTATE_UINT32(ucr1, IMXSerialState),
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VMSTATE_UINT32(uts1, IMXSerialState),
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VMSTATE_UINT32(onems, IMXSerialState),
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VMSTATE_UINT32(ufcr, IMXSerialState),
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VMSTATE_UINT32(ubmr, IMXSerialState),
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VMSTATE_UINT32(ubrc, IMXSerialState),
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VMSTATE_UINT32(ucr3, IMXSerialState),
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2018-03-16 03:11:41 +08:00
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VMSTATE_UINT32(ucr4, IMXSerialState),
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2012-07-04 18:43:33 +08:00
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VMSTATE_END_OF_LIST()
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},
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};
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static void imx_update(IMXSerialState *s)
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{
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2018-03-16 03:11:40 +08:00
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uint32_t usr1;
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uint32_t usr2;
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uint32_t mask;
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2012-07-04 18:43:33 +08:00
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2018-03-16 03:11:40 +08:00
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/*
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* Lucky for us TRDY and RRDY has the same offset in both USR1 and
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* UCR1, so we can get away with something as simple as the
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* following:
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*/
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usr1 = s->usr1 & s->ucr1 & (USR1_TRDY | USR1_RRDY);
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/*
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* Bits that we want in USR2 are not as conveniently laid out,
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* unfortunately.
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*/
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mask = (s->ucr1 & UCR1_TXMPTYEN) ? USR2_TXFE : 0;
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2018-03-16 03:11:41 +08:00
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/*
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* TCEN and TXDC are both bit 3
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2018-08-20 18:24:31 +08:00
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* RDR and DREN are both bit 0
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2018-03-16 03:11:41 +08:00
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*/
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2018-08-20 18:24:31 +08:00
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mask |= s->ucr4 & (UCR4_TCEN | UCR4_DREN);
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2018-03-16 03:11:41 +08:00
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2018-03-16 03:11:40 +08:00
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usr2 = s->usr2 & mask;
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2012-07-04 18:43:33 +08:00
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2018-03-16 03:11:40 +08:00
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qemu_set_irq(s->irq, usr1 || usr2);
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2012-07-04 18:43:33 +08:00
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}
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static void imx_serial_reset(IMXSerialState *s)
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{
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s->usr1 = USR1_TRDY | USR1_RXDS;
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/*
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* Fake attachment of a terminal: assert RTS.
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*/
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s->usr1 |= USR1_RTSS;
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s->usr2 = USR2_TXFE | USR2_TXDC | USR2_DCDIN;
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s->uts1 = UTS1_RXEMPTY | UTS1_TXEMPTY;
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s->ucr1 = 0;
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s->ucr2 = UCR2_SRST;
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s->ucr3 = 0x700;
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s->ubmr = 0;
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s->ubrc = 4;
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s->readbuff = URXD_ERR;
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}
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static void imx_serial_reset_at_boot(DeviceState *dev)
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{
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2013-07-25 04:43:22 +08:00
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IMXSerialState *s = IMX_SERIAL(dev);
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2012-07-04 18:43:33 +08:00
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imx_serial_reset(s);
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/*
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* enable the uart on boot, so messages from the linux decompresser
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* are visible. On real hardware this is done by the boot rom
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* before anything else is loaded.
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*/
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s->ucr1 = UCR1_UARTEN;
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s->ucr2 = UCR2_TXEN;
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}
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2012-10-23 18:30:10 +08:00
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static uint64_t imx_serial_read(void *opaque, hwaddr offset,
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2012-07-04 18:43:33 +08:00
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unsigned size)
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{
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IMXSerialState *s = (IMXSerialState *)opaque;
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uint32_t c;
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2015-10-25 22:16:06 +08:00
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DPRINTF("read(offset=0x%" HWADDR_PRIx ")\n", offset);
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2012-07-04 18:43:33 +08:00
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switch (offset >> 2) {
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case 0x0: /* URXD */
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c = s->readbuff;
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if (!(s->uts1 & UTS1_RXEMPTY)) {
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/* Character is valid */
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c |= URXD_CHARRDY;
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s->usr1 &= ~USR1_RRDY;
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s->usr2 &= ~USR2_RDR;
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s->uts1 |= UTS1_RXEMPTY;
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imx_update(s);
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2016-10-22 17:52:59 +08:00
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qemu_chr_fe_accept_input(&s->chr);
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2012-07-04 18:43:33 +08:00
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}
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return c;
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case 0x20: /* UCR1 */
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return s->ucr1;
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case 0x21: /* UCR2 */
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return s->ucr2;
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case 0x25: /* USR1 */
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return s->usr1;
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case 0x26: /* USR2 */
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return s->usr2;
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case 0x2A: /* BRM Modulator */
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return s->ubmr;
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case 0x2B: /* Baud Rate Count */
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return s->ubrc;
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case 0x2d: /* Test register */
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return s->uts1;
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case 0x24: /* UFCR */
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return s->ufcr;
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case 0x2c:
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return s->onems;
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case 0x22: /* UCR3 */
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return s->ucr3;
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case 0x23: /* UCR4 */
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2018-03-16 03:11:41 +08:00
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return s->ucr4;
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2012-07-04 18:43:33 +08:00
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case 0x29: /* BRM Incremental */
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return 0x0; /* TODO */
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default:
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2015-10-25 22:16:06 +08:00
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
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2012-07-04 18:43:33 +08:00
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return 0;
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}
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}
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2012-10-23 18:30:10 +08:00
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static void imx_serial_write(void *opaque, hwaddr offset,
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2015-08-13 18:26:19 +08:00
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uint64_t value, unsigned size)
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2012-07-04 18:43:33 +08:00
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{
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IMXSerialState *s = (IMXSerialState *)opaque;
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2016-12-07 21:20:22 +08:00
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Chardev *chr = qemu_chr_fe_get_driver(&s->chr);
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2012-07-04 18:43:33 +08:00
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unsigned char ch;
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2015-10-25 22:16:06 +08:00
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DPRINTF("write(offset=0x%" HWADDR_PRIx ", value = 0x%x) to %s\n",
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2016-10-22 17:52:55 +08:00
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offset, (unsigned int)value, chr ? chr->label : "NODEV");
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2012-07-04 18:43:33 +08:00
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switch (offset >> 2) {
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case 0x10: /* UTXD */
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ch = value;
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if (s->ucr2 & UCR2_TXEN) {
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2016-10-22 17:52:59 +08:00
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/* XXX this blocks entire thread. Rewrite to use
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* qemu_chr_fe_write and background I/O callbacks */
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qemu_chr_fe_write_all(&s->chr, &ch, 1);
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2012-07-04 18:43:33 +08:00
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s->usr1 &= ~USR1_TRDY;
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2018-03-16 03:11:41 +08:00
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s->usr2 &= ~USR2_TXDC;
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2012-07-04 18:43:33 +08:00
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imx_update(s);
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s->usr1 |= USR1_TRDY;
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2018-03-16 03:11:41 +08:00
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s->usr2 |= USR2_TXDC;
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2012-07-04 18:43:33 +08:00
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imx_update(s);
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}
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break;
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case 0x20: /* UCR1 */
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s->ucr1 = value & 0xffff;
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2015-10-25 22:16:06 +08:00
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2012-07-04 18:43:33 +08:00
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DPRINTF("write(ucr1=%x)\n", (unsigned int)value);
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2015-10-25 22:16:06 +08:00
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2012-07-04 18:43:33 +08:00
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imx_update(s);
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break;
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case 0x21: /* UCR2 */
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/*
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* Only a few bits in control register 2 are implemented as yet.
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* If it's intended to use a real serial device as a back-end, this
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* register will have to be implemented more fully.
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*/
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if (!(value & UCR2_SRST)) {
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imx_serial_reset(s);
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imx_update(s);
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value |= UCR2_SRST;
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}
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if (value & UCR2_RXEN) {
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if (!(s->ucr2 & UCR2_RXEN)) {
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2016-10-22 17:52:59 +08:00
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qemu_chr_fe_accept_input(&s->chr);
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2012-07-04 18:43:33 +08:00
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}
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}
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s->ucr2 = value & 0xffff;
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break;
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case 0x25: /* USR1 */
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value &= USR1_AWAKE | USR1_AIRINT | USR1_DTRD | USR1_AGTIM |
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2015-08-13 18:26:19 +08:00
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USR1_FRAMERR | USR1_ESCF | USR1_RTSD | USR1_PARTYER;
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2012-07-04 18:43:33 +08:00
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s->usr1 &= ~value;
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break;
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case 0x26: /* USR2 */
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2015-08-13 18:26:19 +08:00
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/*
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* Writing 1 to some bits clears them; all other
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* values are ignored
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*/
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2012-07-04 18:43:33 +08:00
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value &= USR2_ADET | USR2_DTRF | USR2_IDLE | USR2_ACST |
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2015-08-13 18:26:19 +08:00
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USR2_RIDELT | USR2_IRINT | USR2_WAKE |
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USR2_DCDDELT | USR2_RTSF | USR2_BRCD | USR2_ORE;
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2012-07-04 18:43:33 +08:00
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s->usr2 &= ~value;
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break;
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2015-08-13 18:26:19 +08:00
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/*
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* Linux expects to see what it writes to these registers
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* We don't currently alter the baud rate
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*/
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2012-07-04 18:43:33 +08:00
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case 0x29: /* UBIR */
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s->ubrc = value & 0xffff;
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break;
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case 0x2a: /* UBMR */
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s->ubmr = value & 0xffff;
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break;
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case 0x2c: /* One ms reg */
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s->onems = value & 0xffff;
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break;
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case 0x24: /* FIFO control register */
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s->ufcr = value & 0xffff;
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break;
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case 0x22: /* UCR3 */
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s->ucr3 = value & 0xffff;
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break;
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case 0x23: /* UCR4 */
|
2018-03-16 03:11:41 +08:00
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s->ucr4 = value & 0xffff;
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imx_update(s);
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break;
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case 0x2d: /* UTS1 */
|
2015-10-25 22:16:06 +08:00
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qemu_log_mask(LOG_UNIMP, "[%s]%s: Unimplemented reg 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
|
2012-07-04 18:43:33 +08:00
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/* TODO */
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break;
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default:
|
2015-10-25 22:16:06 +08:00
|
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qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at offset 0x%"
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HWADDR_PRIx "\n", TYPE_IMX_SERIAL, __func__, offset);
|
2012-07-04 18:43:33 +08:00
|
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}
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}
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|
|
static int imx_can_receive(void *opaque)
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|
|
|
{
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|
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IMXSerialState *s = (IMXSerialState *)opaque;
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|
return !(s->usr1 & USR1_RRDY);
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}
|
|
|
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|
|
static void imx_put_data(void *opaque, uint32_t value)
|
|
|
|
{
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|
|
|
IMXSerialState *s = (IMXSerialState *)opaque;
|
2015-10-25 22:16:06 +08:00
|
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|
2012-07-04 18:43:33 +08:00
|
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|
DPRINTF("received char\n");
|
2015-10-25 22:16:06 +08:00
|
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|
2012-07-04 18:43:33 +08:00
|
|
|
s->usr1 |= USR1_RRDY;
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|
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s->usr2 |= USR2_RDR;
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|
|
s->uts1 &= ~UTS1_RXEMPTY;
|
|
|
|
s->readbuff = value;
|
2018-03-24 02:26:45 +08:00
|
|
|
if (value & URXD_BRK) {
|
|
|
|
s->usr2 |= USR2_BRCD;
|
|
|
|
}
|
2012-07-04 18:43:33 +08:00
|
|
|
imx_update(s);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void imx_receive(void *opaque, const uint8_t *buf, int size)
|
|
|
|
{
|
|
|
|
imx_put_data(opaque, *buf);
|
|
|
|
}
|
|
|
|
|
chardev: Use QEMUChrEvent enum in IOEventHandler typedef
The Chardev events are listed in the QEMUChrEvent enum.
By using the enum in the IOEventHandler typedef we:
- make the IOEventHandler type more explicit (this handler
process out-of-band information, while the IOReadHandler
is in-band),
- help static code analyzers.
This patch was produced with the following spatch script:
@match@
expression backend, opaque, context, set_open;
identifier fd_can_read, fd_read, fd_event, be_change;
@@
qemu_chr_fe_set_handlers(backend, fd_can_read, fd_read, fd_event,
be_change, opaque, context, set_open);
@depends on match@
identifier opaque, event;
identifier match.fd_event;
@@
static
-void fd_event(void *opaque, int event)
+void fd_event(void *opaque, QEMUChrEvent event)
{
...
}
Then the typedef was modified manually in
include/chardev/char-fe.h.
Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Corey Minyard <cminyard@mvista.com>
Acked-by: Cornelia Huck <cohuck@redhat.com>
Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20191218172009.8868-15-philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
2019-12-19 01:20:09 +08:00
|
|
|
static void imx_event(void *opaque, QEMUChrEvent event)
|
2012-07-04 18:43:33 +08:00
|
|
|
{
|
|
|
|
if (event == CHR_EVENT_BREAK) {
|
2018-03-24 02:26:45 +08:00
|
|
|
imx_put_data(opaque, URXD_BRK | URXD_FRMERR | URXD_ERR);
|
2012-07-04 18:43:33 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
|
|
|
|
static const struct MemoryRegionOps imx_serial_ops = {
|
|
|
|
.read = imx_serial_read,
|
|
|
|
.write = imx_serial_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
|
|
|
};
|
|
|
|
|
2015-08-13 18:26:19 +08:00
|
|
|
static void imx_serial_realize(DeviceState *dev, Error **errp)
|
2012-07-04 18:43:33 +08:00
|
|
|
{
|
2013-07-25 04:43:22 +08:00
|
|
|
IMXSerialState *s = IMX_SERIAL(dev);
|
2012-07-04 18:43:33 +08:00
|
|
|
|
2016-10-22 17:52:59 +08:00
|
|
|
DPRINTF("char dev for uart: %p\n", qemu_chr_fe_get_driver(&s->chr));
|
|
|
|
|
|
|
|
qemu_chr_fe_set_handlers(&s->chr, imx_can_receive, imx_receive,
|
2017-07-06 20:08:49 +08:00
|
|
|
imx_event, NULL, s, NULL, true);
|
2015-08-13 18:26:19 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void imx_serial_init(Object *obj)
|
|
|
|
{
|
|
|
|
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
|
|
|
|
IMXSerialState *s = IMX_SERIAL(obj);
|
2012-07-04 18:43:33 +08:00
|
|
|
|
2015-08-13 18:26:19 +08:00
|
|
|
memory_region_init_io(&s->iomem, obj, &imx_serial_ops, s,
|
|
|
|
TYPE_IMX_SERIAL, 0x1000);
|
|
|
|
sysbus_init_mmio(sbd, &s->iomem);
|
|
|
|
sysbus_init_irq(sbd, &s->irq);
|
2012-07-04 18:43:33 +08:00
|
|
|
}
|
|
|
|
|
2015-08-13 18:26:19 +08:00
|
|
|
static Property imx_serial_properties[] = {
|
2012-07-04 18:43:33 +08:00
|
|
|
DEFINE_PROP_CHR("chardev", IMXSerialState, chr),
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
static void imx_serial_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
|
|
|
|
2015-08-13 18:26:19 +08:00
|
|
|
dc->realize = imx_serial_realize;
|
2012-07-04 18:43:33 +08:00
|
|
|
dc->vmsd = &vmstate_imx_serial;
|
|
|
|
dc->reset = imx_serial_reset_at_boot;
|
2013-07-29 22:17:45 +08:00
|
|
|
set_bit(DEVICE_CATEGORY_INPUT, dc->categories);
|
2012-07-04 18:43:33 +08:00
|
|
|
dc->desc = "i.MX series UART";
|
2020-01-10 23:30:32 +08:00
|
|
|
device_class_set_props(dc, imx_serial_properties);
|
2012-07-04 18:43:33 +08:00
|
|
|
}
|
|
|
|
|
2013-01-10 23:19:07 +08:00
|
|
|
static const TypeInfo imx_serial_info = {
|
2015-08-13 18:26:19 +08:00
|
|
|
.name = TYPE_IMX_SERIAL,
|
|
|
|
.parent = TYPE_SYS_BUS_DEVICE,
|
|
|
|
.instance_size = sizeof(IMXSerialState),
|
|
|
|
.instance_init = imx_serial_init,
|
|
|
|
.class_init = imx_serial_class_init,
|
2012-07-04 18:43:33 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static void imx_serial_register_types(void)
|
|
|
|
{
|
|
|
|
type_register_static(&imx_serial_info);
|
|
|
|
}
|
|
|
|
|
|
|
|
type_init(imx_serial_register_types)
|