mirror of https://gitee.com/openkylin/qemu.git
83 lines
3.8 KiB
C
83 lines
3.8 KiB
C
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#ifndef HW_USB_EHCI_REGS_H
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#define HW_USB_EHCI_REGS_H 1
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/* Capability Registers Base Address - section 2.2 */
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#define CAPLENGTH 0x0000 /* 1-byte, 0x0001 reserved */
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#define HCIVERSION 0x0002 /* 2-bytes, i/f version # */
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#define HCSPARAMS 0x0004 /* 4-bytes, structural params */
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#define HCCPARAMS 0x0008 /* 4-bytes, capability params */
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#define EECP HCCPARAMS + 1
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#define HCSPPORTROUTE1 0x000c
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#define HCSPPORTROUTE2 0x0010
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#define USBCMD 0x0000
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#define USBCMD_RUNSTOP (1 << 0) // run / Stop
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#define USBCMD_HCRESET (1 << 1) // HC Reset
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#define USBCMD_FLS (3 << 2) // Frame List Size
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#define USBCMD_FLS_SH 2 // Frame List Size Shift
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#define USBCMD_PSE (1 << 4) // Periodic Schedule Enable
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#define USBCMD_ASE (1 << 5) // Asynch Schedule Enable
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#define USBCMD_IAAD (1 << 6) // Int Asynch Advance Doorbell
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#define USBCMD_LHCR (1 << 7) // Light Host Controller Reset
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#define USBCMD_ASPMC (3 << 8) // Async Sched Park Mode Count
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#define USBCMD_ASPME (1 << 11) // Async Sched Park Mode Enable
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#define USBCMD_ITC (0x7f << 16) // Int Threshold Control
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#define USBCMD_ITC_SH 16 // Int Threshold Control Shift
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#define USBSTS 0x0004
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#define USBSTS_RO_MASK 0x0000003f
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#define USBSTS_INT (1 << 0) // USB Interrupt
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#define USBSTS_ERRINT (1 << 1) // Error Interrupt
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#define USBSTS_PCD (1 << 2) // Port Change Detect
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#define USBSTS_FLR (1 << 3) // Frame List Rollover
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#define USBSTS_HSE (1 << 4) // Host System Error
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#define USBSTS_IAA (1 << 5) // Interrupt on Async Advance
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#define USBSTS_HALT (1 << 12) // HC Halted
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#define USBSTS_REC (1 << 13) // Reclamation
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#define USBSTS_PSS (1 << 14) // Periodic Schedule Status
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#define USBSTS_ASS (1 << 15) // Asynchronous Schedule Status
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/*
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* Interrupt enable bits correspond to the interrupt active bits in USBSTS
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* so no need to redefine here.
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*/
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#define USBINTR 0x0008
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#define USBINTR_MASK 0x0000003f
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#define FRINDEX 0x000c
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#define CTRLDSSEGMENT 0x0010
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#define PERIODICLISTBASE 0x0014
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#define ASYNCLISTADDR 0x0018
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#define ASYNCLISTADDR_MASK 0xffffffe0
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#define CONFIGFLAG 0x0040
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/*
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* Bits that are reserved or are read-only are masked out of values
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* written to us by software
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*/
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#define PORTSC_RO_MASK 0x007001c0
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#define PORTSC_RWC_MASK 0x0000002a
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#define PORTSC_WKOC_E (1 << 22) // Wake on Over Current Enable
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#define PORTSC_WKDS_E (1 << 21) // Wake on Disconnect Enable
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#define PORTSC_WKCN_E (1 << 20) // Wake on Connect Enable
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#define PORTSC_PTC (15 << 16) // Port Test Control
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#define PORTSC_PTC_SH 16 // Port Test Control shift
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#define PORTSC_PIC (3 << 14) // Port Indicator Control
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#define PORTSC_PIC_SH 14 // Port Indicator Control Shift
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#define PORTSC_POWNER (1 << 13) // Port Owner
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#define PORTSC_PPOWER (1 << 12) // Port Power
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#define PORTSC_LINESTAT (3 << 10) // Port Line Status
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#define PORTSC_LINESTAT_SH 10 // Port Line Status Shift
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#define PORTSC_PRESET (1 << 8) // Port Reset
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#define PORTSC_SUSPEND (1 << 7) // Port Suspend
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#define PORTSC_FPRES (1 << 6) // Force Port Resume
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#define PORTSC_OCC (1 << 5) // Over Current Change
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#define PORTSC_OCA (1 << 4) // Over Current Active
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#define PORTSC_PEDC (1 << 3) // Port Enable/Disable Change
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#define PORTSC_PED (1 << 2) // Port Enable/Disable
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#define PORTSC_CSC (1 << 1) // Connect Status Change
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#define PORTSC_CONNECT (1 << 0) // Current Connect Status
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#endif /* HW_USB_EHCI_REGS_H */
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