2007-09-17 05:08:06 +08:00
|
|
|
/*
|
2007-06-03 19:13:39 +08:00
|
|
|
* Motorola ColdFire MCF5208 SoC emulation.
|
|
|
|
*
|
|
|
|
* Copyright (c) 2007 CodeSourcery.
|
|
|
|
*
|
2011-06-26 10:21:35 +08:00
|
|
|
* This code is licensed under the GPL
|
2007-06-03 19:13:39 +08:00
|
|
|
*/
|
2013-02-04 22:40:22 +08:00
|
|
|
#include "hw/hw.h"
|
2013-02-06 00:06:20 +08:00
|
|
|
#include "hw/m68k/mcf.h"
|
2012-12-18 01:20:00 +08:00
|
|
|
#include "qemu/timer.h"
|
2013-02-04 22:40:22 +08:00
|
|
|
#include "hw/ptimer.h"
|
2012-12-18 01:20:04 +08:00
|
|
|
#include "sysemu/sysemu.h"
|
2013-07-30 00:47:21 +08:00
|
|
|
#include "sysemu/qtest.h"
|
2012-10-24 14:43:34 +08:00
|
|
|
#include "net/net.h"
|
2013-02-04 22:40:22 +08:00
|
|
|
#include "hw/boards.h"
|
|
|
|
#include "hw/loader.h"
|
2009-09-20 22:58:02 +08:00
|
|
|
#include "elf.h"
|
2012-12-18 01:19:49 +08:00
|
|
|
#include "exec/address-spaces.h"
|
2007-06-03 19:13:39 +08:00
|
|
|
|
|
|
|
#define SYS_FREQ 66000000
|
|
|
|
|
|
|
|
#define PCSR_EN 0x0001
|
|
|
|
#define PCSR_RLD 0x0002
|
|
|
|
#define PCSR_PIF 0x0004
|
|
|
|
#define PCSR_PIE 0x0008
|
|
|
|
#define PCSR_OVW 0x0010
|
|
|
|
#define PCSR_DBG 0x0020
|
|
|
|
#define PCSR_DOZE 0x0040
|
|
|
|
#define PCSR_PRE_SHIFT 8
|
|
|
|
#define PCSR_PRE_MASK 0x0f00
|
|
|
|
|
|
|
|
typedef struct {
|
2011-08-09 02:21:47 +08:00
|
|
|
MemoryRegion iomem;
|
2007-06-03 19:13:39 +08:00
|
|
|
qemu_irq irq;
|
|
|
|
ptimer_state *timer;
|
|
|
|
uint16_t pcsr;
|
|
|
|
uint16_t pmr;
|
|
|
|
uint16_t pcntr;
|
|
|
|
} m5208_timer_state;
|
|
|
|
|
|
|
|
static void m5208_timer_update(m5208_timer_state *s)
|
|
|
|
{
|
|
|
|
if ((s->pcsr & (PCSR_PIE | PCSR_PIF)) == (PCSR_PIE | PCSR_PIF))
|
|
|
|
qemu_irq_raise(s->irq);
|
|
|
|
else
|
|
|
|
qemu_irq_lower(s->irq);
|
|
|
|
}
|
|
|
|
|
2012-10-23 18:30:10 +08:00
|
|
|
static void m5208_timer_write(void *opaque, hwaddr offset,
|
2011-08-09 02:21:47 +08:00
|
|
|
uint64_t value, unsigned size)
|
2007-06-03 19:13:39 +08:00
|
|
|
{
|
2008-12-02 02:59:50 +08:00
|
|
|
m5208_timer_state *s = (m5208_timer_state *)opaque;
|
2007-06-03 19:13:39 +08:00
|
|
|
int prescale;
|
|
|
|
int limit;
|
|
|
|
switch (offset) {
|
|
|
|
case 0:
|
|
|
|
/* The PIF bit is set-to-clear. */
|
|
|
|
if (value & PCSR_PIF) {
|
|
|
|
s->pcsr &= ~PCSR_PIF;
|
|
|
|
value &= ~PCSR_PIF;
|
|
|
|
}
|
|
|
|
/* Avoid frobbing the timer if we're just twiddling IRQ bits. */
|
|
|
|
if (((s->pcsr ^ value) & ~PCSR_PIE) == 0) {
|
|
|
|
s->pcsr = value;
|
|
|
|
m5208_timer_update(s);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (s->pcsr & PCSR_EN)
|
|
|
|
ptimer_stop(s->timer);
|
|
|
|
|
|
|
|
s->pcsr = value;
|
|
|
|
|
|
|
|
prescale = 1 << ((s->pcsr & PCSR_PRE_MASK) >> PCSR_PRE_SHIFT);
|
|
|
|
ptimer_set_freq(s->timer, (SYS_FREQ / 2) / prescale);
|
|
|
|
if (s->pcsr & PCSR_RLD)
|
|
|
|
limit = s->pmr;
|
2007-06-03 20:54:38 +08:00
|
|
|
else
|
|
|
|
limit = 0xffff;
|
2007-06-03 19:13:39 +08:00
|
|
|
ptimer_set_limit(s->timer, limit, 0);
|
|
|
|
|
|
|
|
if (s->pcsr & PCSR_EN)
|
|
|
|
ptimer_run(s->timer, 0);
|
|
|
|
break;
|
|
|
|
case 2:
|
|
|
|
s->pmr = value;
|
|
|
|
s->pcsr &= ~PCSR_PIF;
|
2007-06-03 20:54:38 +08:00
|
|
|
if ((s->pcsr & PCSR_RLD) == 0) {
|
|
|
|
if (s->pcsr & PCSR_OVW)
|
|
|
|
ptimer_set_count(s->timer, value);
|
|
|
|
} else {
|
|
|
|
ptimer_set_limit(s->timer, value, s->pcsr & PCSR_OVW);
|
|
|
|
}
|
2007-06-03 19:13:39 +08:00
|
|
|
break;
|
|
|
|
case 4:
|
|
|
|
break;
|
|
|
|
default:
|
2009-05-08 09:35:15 +08:00
|
|
|
hw_error("m5208_timer_write: Bad offset 0x%x\n", (int)offset);
|
2008-12-02 02:59:50 +08:00
|
|
|
break;
|
2007-06-03 19:13:39 +08:00
|
|
|
}
|
|
|
|
m5208_timer_update(s);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void m5208_timer_trigger(void *opaque)
|
|
|
|
{
|
|
|
|
m5208_timer_state *s = (m5208_timer_state *)opaque;
|
|
|
|
s->pcsr |= PCSR_PIF;
|
|
|
|
m5208_timer_update(s);
|
|
|
|
}
|
|
|
|
|
2012-10-23 18:30:10 +08:00
|
|
|
static uint64_t m5208_timer_read(void *opaque, hwaddr addr,
|
2011-08-09 02:21:47 +08:00
|
|
|
unsigned size)
|
2008-12-02 02:59:50 +08:00
|
|
|
{
|
|
|
|
m5208_timer_state *s = (m5208_timer_state *)opaque;
|
|
|
|
switch (addr) {
|
|
|
|
case 0:
|
|
|
|
return s->pcsr;
|
|
|
|
case 2:
|
|
|
|
return s->pmr;
|
|
|
|
case 4:
|
|
|
|
return ptimer_get_count(s->timer);
|
|
|
|
default:
|
2009-05-08 09:35:15 +08:00
|
|
|
hw_error("m5208_timer_read: Bad offset 0x%x\n", (int)addr);
|
2008-12-02 02:59:50 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2011-08-09 02:21:47 +08:00
|
|
|
static const MemoryRegionOps m5208_timer_ops = {
|
|
|
|
.read = m5208_timer_read,
|
|
|
|
.write = m5208_timer_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2008-12-02 02:59:50 +08:00
|
|
|
};
|
|
|
|
|
2012-10-23 18:30:10 +08:00
|
|
|
static uint64_t m5208_sys_read(void *opaque, hwaddr addr,
|
2011-08-09 02:21:47 +08:00
|
|
|
unsigned size)
|
2007-06-03 19:13:39 +08:00
|
|
|
{
|
|
|
|
switch (addr) {
|
2008-12-02 02:59:50 +08:00
|
|
|
case 0x110: /* SDCS0 */
|
2007-06-03 19:13:39 +08:00
|
|
|
{
|
|
|
|
int n;
|
|
|
|
for (n = 0; n < 32; n++) {
|
|
|
|
if (ram_size < (2u << n))
|
|
|
|
break;
|
|
|
|
}
|
|
|
|
return (n - 1) | 0x40000000;
|
|
|
|
}
|
2008-12-02 02:59:50 +08:00
|
|
|
case 0x114: /* SDCS1 */
|
2007-06-03 19:13:39 +08:00
|
|
|
return 0;
|
|
|
|
|
|
|
|
default:
|
2009-05-08 09:35:15 +08:00
|
|
|
hw_error("m5208_sys_read: Bad offset 0x%x\n", (int)addr);
|
2007-06-03 19:13:39 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2012-10-23 18:30:10 +08:00
|
|
|
static void m5208_sys_write(void *opaque, hwaddr addr,
|
2011-08-09 02:21:47 +08:00
|
|
|
uint64_t value, unsigned size)
|
2007-06-03 19:13:39 +08:00
|
|
|
{
|
2009-05-08 09:35:15 +08:00
|
|
|
hw_error("m5208_sys_write: Bad offset 0x%x\n", (int)addr);
|
2007-06-03 19:13:39 +08:00
|
|
|
}
|
|
|
|
|
2011-08-09 02:21:47 +08:00
|
|
|
static const MemoryRegionOps m5208_sys_ops = {
|
|
|
|
.read = m5208_sys_read,
|
|
|
|
.write = m5208_sys_write,
|
|
|
|
.endianness = DEVICE_NATIVE_ENDIAN,
|
2007-06-03 19:13:39 +08:00
|
|
|
};
|
|
|
|
|
2011-08-09 02:21:47 +08:00
|
|
|
static void mcf5208_sys_init(MemoryRegion *address_space, qemu_irq *pic)
|
2007-06-03 19:13:39 +08:00
|
|
|
{
|
2011-08-09 02:21:47 +08:00
|
|
|
MemoryRegion *iomem = g_new(MemoryRegion, 1);
|
2008-12-02 02:59:50 +08:00
|
|
|
m5208_timer_state *s;
|
2007-06-03 19:13:39 +08:00
|
|
|
QEMUBH *bh;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
/* SDRAMC. */
|
2013-06-06 17:41:28 +08:00
|
|
|
memory_region_init_io(iomem, NULL, &m5208_sys_ops, NULL, "m5208-sys", 0x00004000);
|
2011-08-09 02:21:47 +08:00
|
|
|
memory_region_add_subregion(address_space, 0xfc0a8000, iomem);
|
2007-06-03 19:13:39 +08:00
|
|
|
/* Timers. */
|
|
|
|
for (i = 0; i < 2; i++) {
|
2011-08-21 11:09:37 +08:00
|
|
|
s = (m5208_timer_state *)g_malloc0(sizeof(m5208_timer_state));
|
2008-12-02 02:59:50 +08:00
|
|
|
bh = qemu_bh_new(m5208_timer_trigger, s);
|
|
|
|
s->timer = ptimer_init(bh);
|
2013-06-06 17:41:28 +08:00
|
|
|
memory_region_init_io(&s->iomem, NULL, &m5208_timer_ops, s,
|
2011-08-09 02:21:47 +08:00
|
|
|
"m5208-timer", 0x00004000);
|
|
|
|
memory_region_add_subregion(address_space, 0xfc080000 + 0x4000 * i,
|
|
|
|
&s->iomem);
|
2008-12-02 02:59:50 +08:00
|
|
|
s->irq = pic[4 + i];
|
2007-06-03 19:13:39 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2014-05-07 22:42:57 +08:00
|
|
|
static void mcf5208evb_init(MachineState *machine)
|
2007-06-03 19:13:39 +08:00
|
|
|
{
|
2014-05-07 22:42:57 +08:00
|
|
|
ram_addr_t ram_size = machine->ram_size;
|
|
|
|
const char *cpu_model = machine->cpu_model;
|
|
|
|
const char *kernel_filename = machine->kernel_filename;
|
2013-01-18 21:15:09 +08:00
|
|
|
M68kCPU *cpu;
|
2012-03-14 08:38:23 +08:00
|
|
|
CPUM68KState *env;
|
2007-06-03 19:13:39 +08:00
|
|
|
int kernel_size;
|
|
|
|
uint64_t elf_entry;
|
2012-10-23 18:30:10 +08:00
|
|
|
hwaddr entry;
|
2007-06-03 19:13:39 +08:00
|
|
|
qemu_irq *pic;
|
2011-08-09 02:21:47 +08:00
|
|
|
MemoryRegion *address_space_mem = get_system_memory();
|
|
|
|
MemoryRegion *ram = g_new(MemoryRegion, 1);
|
|
|
|
MemoryRegion *sram = g_new(MemoryRegion, 1);
|
2007-06-03 19:13:39 +08:00
|
|
|
|
2013-01-18 21:15:09 +08:00
|
|
|
if (!cpu_model) {
|
2007-06-03 19:13:39 +08:00
|
|
|
cpu_model = "m5208";
|
2013-01-18 21:15:09 +08:00
|
|
|
}
|
|
|
|
cpu = cpu_m68k_init(cpu_model);
|
|
|
|
if (!cpu) {
|
2007-11-10 23:15:54 +08:00
|
|
|
fprintf(stderr, "Unable to find m68k CPU definition\n");
|
|
|
|
exit(1);
|
2007-06-03 19:13:39 +08:00
|
|
|
}
|
2013-01-18 21:15:09 +08:00
|
|
|
env = &cpu->env;
|
2007-06-03 19:13:39 +08:00
|
|
|
|
|
|
|
/* Initialize CPU registers. */
|
|
|
|
env->vbr = 0;
|
|
|
|
/* TODO: Configure BARs. */
|
|
|
|
|
2009-04-10 04:05:49 +08:00
|
|
|
/* DRAM at 0x40000000 */
|
2015-03-25 06:11:03 +08:00
|
|
|
memory_region_allocate_system_memory(ram, NULL, "mcf5208.ram", ram_size);
|
2011-08-09 02:21:47 +08:00
|
|
|
memory_region_add_subregion(address_space_mem, 0x40000000, ram);
|
2007-06-03 19:13:39 +08:00
|
|
|
|
|
|
|
/* Internal SRAM. */
|
2014-09-09 13:27:55 +08:00
|
|
|
memory_region_init_ram(sram, NULL, "mcf5208.sram", 16384, &error_abort);
|
2011-12-20 21:59:12 +08:00
|
|
|
vmstate_register_ram_global(sram);
|
2011-08-09 02:21:47 +08:00
|
|
|
memory_region_add_subregion(address_space_mem, 0x80000000, sram);
|
2007-06-03 19:13:39 +08:00
|
|
|
|
|
|
|
/* Internal peripherals. */
|
2013-01-18 21:15:09 +08:00
|
|
|
pic = mcf_intc_init(address_space_mem, 0xfc048000, cpu);
|
2007-06-03 19:13:39 +08:00
|
|
|
|
2011-11-24 21:31:13 +08:00
|
|
|
mcf_uart_mm_init(address_space_mem, 0xfc060000, pic[26], serial_hds[0]);
|
|
|
|
mcf_uart_mm_init(address_space_mem, 0xfc064000, pic[27], serial_hds[1]);
|
|
|
|
mcf_uart_mm_init(address_space_mem, 0xfc068000, pic[28], serial_hds[2]);
|
2007-06-03 19:13:39 +08:00
|
|
|
|
2011-08-09 02:21:47 +08:00
|
|
|
mcf5208_sys_init(address_space_mem, pic);
|
2007-06-03 19:13:39 +08:00
|
|
|
|
2007-06-04 08:31:01 +08:00
|
|
|
if (nb_nics > 1) {
|
|
|
|
fprintf(stderr, "Too many NICs\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
2012-07-24 23:35:11 +08:00
|
|
|
if (nd_table[0].used)
|
2011-11-24 21:31:14 +08:00
|
|
|
mcf_fec_init(address_space_mem, &nd_table[0],
|
|
|
|
0xfc030000, pic + 36);
|
2007-06-04 08:31:01 +08:00
|
|
|
|
2007-06-03 19:13:39 +08:00
|
|
|
/* 0xfc000000 SCM. */
|
|
|
|
/* 0xfc004000 XBS. */
|
|
|
|
/* 0xfc008000 FlexBus CS. */
|
2007-06-04 08:31:01 +08:00
|
|
|
/* 0xfc030000 FEC. */
|
2007-06-03 19:13:39 +08:00
|
|
|
/* 0xfc040000 SCM + Power management. */
|
|
|
|
/* 0xfc044000 eDMA. */
|
|
|
|
/* 0xfc048000 INTC. */
|
|
|
|
/* 0xfc058000 I2C. */
|
|
|
|
/* 0xfc05c000 QSPI. */
|
|
|
|
/* 0xfc060000 UART0. */
|
|
|
|
/* 0xfc064000 UART0. */
|
|
|
|
/* 0xfc068000 UART0. */
|
|
|
|
/* 0xfc070000 DMA timers. */
|
|
|
|
/* 0xfc080000 PIT0. */
|
|
|
|
/* 0xfc084000 PIT1. */
|
|
|
|
/* 0xfc088000 EPORT. */
|
|
|
|
/* 0xfc08c000 Watchdog. */
|
|
|
|
/* 0xfc090000 clock module. */
|
|
|
|
/* 0xfc0a0000 CCM + reset. */
|
|
|
|
/* 0xfc0a4000 GPIO. */
|
|
|
|
/* 0xfc0a8000 SDRAM controller. */
|
|
|
|
|
|
|
|
/* Load kernel. */
|
|
|
|
if (!kernel_filename) {
|
2013-07-30 00:47:21 +08:00
|
|
|
if (qtest_enabled()) {
|
|
|
|
return;
|
|
|
|
}
|
2007-06-03 19:13:39 +08:00
|
|
|
fprintf(stderr, "Kernel image must be specified\n");
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
2010-03-15 04:20:59 +08:00
|
|
|
kernel_size = load_elf(kernel_filename, NULL, NULL, &elf_entry,
|
|
|
|
NULL, NULL, 1, ELF_MACHINE, 0);
|
2007-06-03 19:13:39 +08:00
|
|
|
entry = elf_entry;
|
|
|
|
if (kernel_size < 0) {
|
2014-10-19 11:42:22 +08:00
|
|
|
kernel_size = load_uimage(kernel_filename, &entry, NULL, NULL,
|
|
|
|
NULL, NULL);
|
2007-06-03 19:13:39 +08:00
|
|
|
}
|
|
|
|
if (kernel_size < 0) {
|
2009-04-10 04:05:49 +08:00
|
|
|
kernel_size = load_image_targphys(kernel_filename, 0x40000000,
|
|
|
|
ram_size);
|
|
|
|
entry = 0x40000000;
|
2007-06-03 19:13:39 +08:00
|
|
|
}
|
|
|
|
if (kernel_size < 0) {
|
|
|
|
fprintf(stderr, "qemu: could not load kernel '%s'\n", kernel_filename);
|
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
|
|
|
env->pc = entry;
|
|
|
|
}
|
|
|
|
|
2009-05-21 07:38:09 +08:00
|
|
|
static QEMUMachine mcf5208evb_machine = {
|
2008-10-08 04:34:35 +08:00
|
|
|
.name = "mcf5208evb",
|
|
|
|
.desc = "MCF5206EVB",
|
|
|
|
.init = mcf5208evb_init,
|
2009-05-22 09:41:01 +08:00
|
|
|
.is_default = 1,
|
2007-06-03 19:13:39 +08:00
|
|
|
};
|
2009-05-21 07:38:09 +08:00
|
|
|
|
|
|
|
static void mcf5208evb_machine_init(void)
|
|
|
|
{
|
|
|
|
qemu_register_machine(&mcf5208evb_machine);
|
|
|
|
}
|
|
|
|
|
|
|
|
machine_init(mcf5208evb_machine_init);
|