2004-06-06 23:16:19 +08:00
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/*
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* QEMU Cirrus CLGD 54xx VGA Emulator.
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2007-09-17 05:08:06 +08:00
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*
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2004-06-06 23:16:19 +08:00
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* Copyright (c) 2004 Fabrice Bellard
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2007-09-17 05:08:06 +08:00
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*
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2004-06-06 23:16:19 +08:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#if DEPTH == 8
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2017-03-15 18:47:52 +08:00
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#define PUTPIXEL(s, a, c) ROP_OP(s, a, c)
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2004-06-06 23:16:19 +08:00
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#elif DEPTH == 16
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2017-03-15 18:47:52 +08:00
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#define PUTPIXEL(s, a, c) ROP_OP_16(s, a, c)
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2004-06-06 23:16:19 +08:00
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#elif DEPTH == 24
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2017-03-15 18:47:52 +08:00
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#define PUTPIXEL(s, a, c) do { \
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ROP_OP(s, a, c); \
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2017-03-22 15:38:23 +08:00
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ROP_OP(s, a + 1, (c >> 8)); \
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ROP_OP(s, a + 2, (c >> 16)); \
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2017-03-15 18:47:52 +08:00
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} while (0)
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2004-06-06 23:16:19 +08:00
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#elif DEPTH == 32
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2017-03-15 18:47:52 +08:00
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#define PUTPIXEL(s, a, c) ROP_OP_32(s, a, c)
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2004-06-06 23:16:19 +08:00
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#else
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#error unsupported DEPTH
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2007-09-17 16:09:54 +08:00
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#endif
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2004-06-06 23:16:19 +08:00
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2004-06-10 07:12:09 +08:00
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static void
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glue(glue(glue(cirrus_patternfill_, ROP_NAME), _),DEPTH)
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2017-03-15 18:47:52 +08:00
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(CirrusVGAState *s, uint32_t dstaddr,
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2017-03-15 21:28:07 +08:00
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uint32_t srcaddr,
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2007-09-17 05:08:06 +08:00
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int dstpitch, int srcpitch,
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2004-06-10 07:12:09 +08:00
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int bltwidth, int bltheight)
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{
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2017-03-15 18:47:52 +08:00
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uint32_t addr;
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2004-06-10 07:12:09 +08:00
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int x, y, pattern_y, pattern_pitch, pattern_x;
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unsigned int col;
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2017-03-15 21:28:07 +08:00
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uint32_t src1addr;
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2005-04-27 04:49:17 +08:00
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#if DEPTH == 24
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2009-05-04 03:25:16 +08:00
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int skipleft = s->vga.gr[0x2f] & 0x1f;
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2005-04-27 04:49:17 +08:00
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#else
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2009-05-04 03:25:16 +08:00
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int skipleft = (s->vga.gr[0x2f] & 0x07) * (DEPTH / 8);
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2005-04-27 04:49:17 +08:00
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#endif
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2004-06-10 07:12:09 +08:00
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#if DEPTH == 8
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pattern_pitch = 8;
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#elif DEPTH == 16
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pattern_pitch = 16;
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#else
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pattern_pitch = 32;
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#endif
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pattern_y = s->cirrus_blt_srcaddr & 7;
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for(y = 0; y < bltheight; y++) {
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2005-07-03 04:12:37 +08:00
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pattern_x = skipleft;
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2017-03-15 18:47:52 +08:00
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addr = dstaddr + skipleft;
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2017-03-15 21:28:07 +08:00
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src1addr = srcaddr + pattern_y * pattern_pitch;
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2005-04-18 01:56:18 +08:00
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for (x = skipleft; x < bltwidth; x += (DEPTH / 8)) {
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2004-06-10 07:12:09 +08:00
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#if DEPTH == 8
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2017-03-15 21:28:07 +08:00
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col = cirrus_src(s, src1addr + pattern_x);
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2004-06-10 07:12:09 +08:00
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pattern_x = (pattern_x + 1) & 7;
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#elif DEPTH == 16
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2017-03-15 21:28:07 +08:00
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col = cirrus_src16(s, src1addr + pattern_x);
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2004-06-10 07:12:09 +08:00
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pattern_x = (pattern_x + 2) & 15;
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2004-07-06 09:50:49 +08:00
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#elif DEPTH == 24
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{
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2017-03-15 21:28:07 +08:00
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uint32_t src2addr = src1addr + pattern_x * 3;
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col = cirrus_src(s, src2addr) |
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(cirrus_src(s, src2addr + 1) << 8) |
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(cirrus_src(s, src2addr + 2) << 16);
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2004-07-06 09:50:49 +08:00
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pattern_x = (pattern_x + 1) & 7;
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}
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2004-06-10 07:12:09 +08:00
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#else
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2017-03-15 21:28:07 +08:00
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col = cirrus_src32(s, src1addr + pattern_x);
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2004-06-10 07:12:09 +08:00
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pattern_x = (pattern_x + 4) & 31;
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#endif
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2017-03-15 18:47:52 +08:00
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PUTPIXEL(s, addr, col);
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addr += (DEPTH / 8);
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2004-06-10 07:12:09 +08:00
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}
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pattern_y = (pattern_y + 1) & 7;
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2017-03-15 18:47:52 +08:00
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dstaddr += dstpitch;
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2004-06-10 07:12:09 +08:00
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}
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}
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2004-06-08 03:46:45 +08:00
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/* NOTE: srcpitch is ignored */
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2004-06-06 23:16:19 +08:00
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static void
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glue(glue(glue(cirrus_colorexpand_transp_, ROP_NAME), _),DEPTH)
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2017-03-15 18:47:52 +08:00
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(CirrusVGAState *s, uint32_t dstaddr,
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2017-03-15 21:28:07 +08:00
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uint32_t srcaddr,
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2007-09-17 05:08:06 +08:00
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int dstpitch, int srcpitch,
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2004-06-06 23:16:19 +08:00
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int bltwidth, int bltheight)
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{
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2017-03-15 18:47:52 +08:00
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uint32_t addr;
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2004-06-06 23:16:19 +08:00
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int x, y;
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2004-07-06 09:50:49 +08:00
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unsigned bits, bits_xor;
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2004-06-06 23:16:19 +08:00
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unsigned int col;
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unsigned bitmask;
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unsigned index;
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2005-04-27 04:49:17 +08:00
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#if DEPTH == 24
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2009-05-04 03:25:16 +08:00
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int dstskipleft = s->vga.gr[0x2f] & 0x1f;
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2005-04-27 04:49:17 +08:00
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int srcskipleft = dstskipleft / 3;
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#else
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2009-05-04 03:25:16 +08:00
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int srcskipleft = s->vga.gr[0x2f] & 0x07;
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2005-04-18 01:56:18 +08:00
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int dstskipleft = srcskipleft * (DEPTH / 8);
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2005-04-27 04:49:17 +08:00
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#endif
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2004-06-06 23:16:19 +08:00
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2004-07-06 09:50:49 +08:00
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if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) {
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bits_xor = 0xff;
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col = s->cirrus_blt_bgcol;
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} else {
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bits_xor = 0x00;
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col = s->cirrus_blt_fgcol;
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}
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2004-06-06 23:16:19 +08:00
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for(y = 0; y < bltheight; y++) {
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bitmask = 0x80 >> srcskipleft;
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2017-03-15 21:28:07 +08:00
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bits = cirrus_src(s, srcaddr++) ^ bits_xor;
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2017-03-15 18:47:52 +08:00
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addr = dstaddr + dstskipleft;
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2005-04-18 01:56:18 +08:00
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for (x = dstskipleft; x < bltwidth; x += (DEPTH / 8)) {
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2004-06-06 23:16:19 +08:00
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if ((bitmask & 0xff) == 0) {
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bitmask = 0x80;
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2017-03-15 21:28:07 +08:00
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bits = cirrus_src(s, srcaddr++) ^ bits_xor;
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2004-06-06 23:16:19 +08:00
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}
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index = (bits & bitmask);
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if (index) {
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2017-03-15 18:47:52 +08:00
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PUTPIXEL(s, addr, col);
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2004-06-06 23:16:19 +08:00
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}
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2017-03-15 18:47:52 +08:00
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addr += (DEPTH / 8);
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2004-06-06 23:16:19 +08:00
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bitmask >>= 1;
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}
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2017-03-15 18:47:52 +08:00
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dstaddr += dstpitch;
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2004-06-08 03:46:45 +08:00
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}
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}
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static void
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2004-07-06 09:50:49 +08:00
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glue(glue(glue(cirrus_colorexpand_, ROP_NAME), _),DEPTH)
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2017-03-15 18:47:52 +08:00
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(CirrusVGAState *s, uint32_t dstaddr,
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2017-03-15 21:28:07 +08:00
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uint32_t srcaddr,
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2007-09-17 05:08:06 +08:00
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int dstpitch, int srcpitch,
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2004-06-08 03:46:45 +08:00
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int bltwidth, int bltheight)
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{
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2004-07-06 09:50:49 +08:00
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uint32_t colors[2];
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2017-03-15 18:47:52 +08:00
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uint32_t addr;
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2004-06-08 03:46:45 +08:00
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int x, y;
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unsigned bits;
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unsigned int col;
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unsigned bitmask;
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2009-05-04 03:25:16 +08:00
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int srcskipleft = s->vga.gr[0x2f] & 0x07;
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2005-04-18 01:56:18 +08:00
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int dstskipleft = srcskipleft * (DEPTH / 8);
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2004-06-08 03:46:45 +08:00
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2004-07-06 09:50:49 +08:00
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colors[0] = s->cirrus_blt_bgcol;
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colors[1] = s->cirrus_blt_fgcol;
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2004-06-08 03:46:45 +08:00
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for(y = 0; y < bltheight; y++) {
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bitmask = 0x80 >> srcskipleft;
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2017-03-15 21:28:07 +08:00
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bits = cirrus_src(s, srcaddr++);
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2017-03-15 18:47:52 +08:00
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addr = dstaddr + dstskipleft;
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2005-04-18 01:56:18 +08:00
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for (x = dstskipleft; x < bltwidth; x += (DEPTH / 8)) {
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2004-06-08 03:46:45 +08:00
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if ((bitmask & 0xff) == 0) {
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bitmask = 0x80;
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2017-03-15 21:28:07 +08:00
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bits = cirrus_src(s, srcaddr++);
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2004-06-08 03:46:45 +08:00
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}
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2004-07-06 09:50:49 +08:00
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col = colors[!!(bits & bitmask)];
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2017-03-15 18:47:52 +08:00
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PUTPIXEL(s, addr, col);
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addr += (DEPTH / 8);
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2004-07-06 09:50:49 +08:00
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bitmask >>= 1;
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}
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2017-03-15 18:47:52 +08:00
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dstaddr += dstpitch;
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2004-07-06 09:50:49 +08:00
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}
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}
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static void
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glue(glue(glue(cirrus_colorexpand_pattern_transp_, ROP_NAME), _),DEPTH)
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2017-03-15 18:47:52 +08:00
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(CirrusVGAState *s, uint32_t dstaddr,
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2017-03-15 21:28:07 +08:00
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uint32_t srcaddr,
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2007-09-17 05:08:06 +08:00
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int dstpitch, int srcpitch,
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2004-07-06 09:50:49 +08:00
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int bltwidth, int bltheight)
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{
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2017-03-15 18:47:52 +08:00
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uint32_t addr;
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2004-07-06 09:50:49 +08:00
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int x, y, bitpos, pattern_y;
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unsigned int bits, bits_xor;
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unsigned int col;
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2005-04-27 04:49:17 +08:00
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#if DEPTH == 24
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2009-05-04 03:25:16 +08:00
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int dstskipleft = s->vga.gr[0x2f] & 0x1f;
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2005-04-27 04:49:17 +08:00
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int srcskipleft = dstskipleft / 3;
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#else
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2009-05-04 03:25:16 +08:00
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int srcskipleft = s->vga.gr[0x2f] & 0x07;
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2005-04-18 01:56:18 +08:00
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int dstskipleft = srcskipleft * (DEPTH / 8);
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2005-04-27 04:49:17 +08:00
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#endif
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2004-07-06 09:50:49 +08:00
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if (s->cirrus_blt_modeext & CIRRUS_BLTMODEEXT_COLOREXPINV) {
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bits_xor = 0xff;
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col = s->cirrus_blt_bgcol;
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} else {
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bits_xor = 0x00;
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col = s->cirrus_blt_fgcol;
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}
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pattern_y = s->cirrus_blt_srcaddr & 7;
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for(y = 0; y < bltheight; y++) {
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2017-03-15 21:28:07 +08:00
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bits = cirrus_src(s, srcaddr + pattern_y) ^ bits_xor;
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2005-04-18 01:56:18 +08:00
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bitpos = 7 - srcskipleft;
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2017-03-15 18:47:52 +08:00
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addr = dstaddr + dstskipleft;
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2005-04-18 01:56:18 +08:00
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for (x = dstskipleft; x < bltwidth; x += (DEPTH / 8)) {
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2004-07-06 09:50:49 +08:00
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if ((bits >> bitpos) & 1) {
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2017-03-15 18:47:52 +08:00
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PUTPIXEL(s, addr, col);
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2004-06-08 03:46:45 +08:00
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}
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2017-03-15 18:47:52 +08:00
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addr += (DEPTH / 8);
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2004-07-06 09:50:49 +08:00
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bitpos = (bitpos - 1) & 7;
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2004-06-08 03:46:45 +08:00
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}
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2004-07-06 09:50:49 +08:00
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pattern_y = (pattern_y + 1) & 7;
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2017-03-15 18:47:52 +08:00
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dstaddr += dstpitch;
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2004-06-06 23:16:19 +08:00
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}
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}
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static void
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2004-07-06 09:50:49 +08:00
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glue(glue(glue(cirrus_colorexpand_pattern_, ROP_NAME), _),DEPTH)
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2017-03-15 18:47:52 +08:00
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(CirrusVGAState *s, uint32_t dstaddr,
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2017-03-15 21:28:07 +08:00
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uint32_t srcaddr,
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2007-09-17 05:08:06 +08:00
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int dstpitch, int srcpitch,
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2004-06-06 23:16:19 +08:00
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int bltwidth, int bltheight)
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{
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uint32_t colors[2];
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2017-03-15 18:47:52 +08:00
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uint32_t addr;
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2004-07-06 09:50:49 +08:00
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int x, y, bitpos, pattern_y;
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unsigned int bits;
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2004-06-06 23:16:19 +08:00
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unsigned int col;
|
2009-05-04 03:25:16 +08:00
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int srcskipleft = s->vga.gr[0x2f] & 0x07;
|
2005-04-18 01:56:18 +08:00
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int dstskipleft = srcskipleft * (DEPTH / 8);
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2004-06-06 23:16:19 +08:00
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colors[0] = s->cirrus_blt_bgcol;
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colors[1] = s->cirrus_blt_fgcol;
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2004-07-06 09:50:49 +08:00
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pattern_y = s->cirrus_blt_srcaddr & 7;
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2004-06-06 23:16:19 +08:00
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for(y = 0; y < bltheight; y++) {
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2017-03-15 21:28:07 +08:00
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bits = cirrus_src(s, srcaddr + pattern_y);
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2005-04-18 01:56:18 +08:00
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bitpos = 7 - srcskipleft;
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2017-03-15 18:47:52 +08:00
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addr = dstaddr + dstskipleft;
|
2005-04-18 01:56:18 +08:00
|
|
|
for (x = dstskipleft; x < bltwidth; x += (DEPTH / 8)) {
|
2004-07-06 09:50:49 +08:00
|
|
|
col = colors[(bits >> bitpos) & 1];
|
2017-03-15 18:47:52 +08:00
|
|
|
PUTPIXEL(s, addr, col);
|
|
|
|
addr += (DEPTH / 8);
|
2004-07-06 09:50:49 +08:00
|
|
|
bitpos = (bitpos - 1) & 7;
|
2004-06-06 23:16:19 +08:00
|
|
|
}
|
2004-07-06 09:50:49 +08:00
|
|
|
pattern_y = (pattern_y + 1) & 7;
|
2017-03-15 18:47:52 +08:00
|
|
|
dstaddr += dstpitch;
|
2004-06-06 23:16:19 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-09-17 05:08:06 +08:00
|
|
|
static void
|
2004-06-06 23:16:19 +08:00
|
|
|
glue(glue(glue(cirrus_fill_, ROP_NAME), _),DEPTH)
|
|
|
|
(CirrusVGAState *s,
|
2017-03-15 18:47:52 +08:00
|
|
|
uint32_t dstaddr, int dst_pitch,
|
2004-06-06 23:16:19 +08:00
|
|
|
int width, int height)
|
|
|
|
{
|
2017-03-15 18:47:52 +08:00
|
|
|
uint32_t addr;
|
2004-06-06 23:16:19 +08:00
|
|
|
uint32_t col;
|
|
|
|
int x, y;
|
|
|
|
|
|
|
|
col = s->cirrus_blt_fgcol;
|
|
|
|
|
|
|
|
for(y = 0; y < height; y++) {
|
2017-03-15 18:47:52 +08:00
|
|
|
addr = dstaddr;
|
2004-06-06 23:16:19 +08:00
|
|
|
for(x = 0; x < width; x += (DEPTH / 8)) {
|
2017-03-15 18:47:52 +08:00
|
|
|
PUTPIXEL(s, addr, col);
|
|
|
|
addr += (DEPTH / 8);
|
2004-06-06 23:16:19 +08:00
|
|
|
}
|
2017-03-15 18:47:52 +08:00
|
|
|
dstaddr += dst_pitch;
|
2004-06-06 23:16:19 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
#undef DEPTH
|
|
|
|
#undef PUTPIXEL
|