2010-06-29 10:49:29 +08:00
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/*
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* VT82C686B south bridge support
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*
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* Copyright (c) 2008 yajin (yajin@vm-kernel.org)
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* Copyright (c) 2009 chenming (chenming@rdc.faw.com.cn)
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* Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com)
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* This code is licensed under the GNU GPL v2.
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2012-01-14 00:44:23 +08:00
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*
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* Contributions after 2012-01-13 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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2010-06-29 10:49:29 +08:00
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*/
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2013-02-04 22:40:22 +08:00
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#include "hw/hw.h"
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2013-02-06 00:06:20 +08:00
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#include "hw/i386/pc.h"
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#include "hw/isa/vt82c686.h"
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#include "hw/i2c/i2c.h"
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#include "hw/i2c/smbus.h"
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2013-02-04 22:40:22 +08:00
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#include "hw/pci/pci.h"
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2013-02-06 00:06:20 +08:00
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#include "hw/isa/isa.h"
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2013-02-04 22:40:22 +08:00
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#include "hw/sysbus.h"
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2013-02-06 00:06:20 +08:00
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#include "hw/mips/mips.h"
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#include "hw/isa/apm.h"
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#include "hw/acpi/acpi.h"
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#include "hw/i2c/pm_smbus.h"
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2012-12-18 01:20:04 +08:00
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#include "sysemu/sysemu.h"
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2012-12-18 01:20:00 +08:00
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#include "qemu/timer.h"
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2012-12-18 01:19:49 +08:00
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#include "exec/address-spaces.h"
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2010-06-29 10:49:29 +08:00
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//#define DEBUG_VT82C686B
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#ifdef DEBUG_VT82C686B
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#define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__)
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#else
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#define DPRINTF(fmt, ...)
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#endif
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typedef struct SuperIOConfig
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{
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uint8_t config[0xff];
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uint8_t index;
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uint8_t data;
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} SuperIOConfig;
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typedef struct VT82C686BState {
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PCIDevice dev;
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2013-06-22 14:06:59 +08:00
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MemoryRegion superio;
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2010-06-29 10:49:29 +08:00
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SuperIOConfig superio_conf;
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} VT82C686BState;
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2013-06-22 14:06:59 +08:00
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static void superio_ioport_writeb(void *opaque, hwaddr addr, uint64_t data,
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unsigned size)
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2010-06-29 10:49:29 +08:00
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{
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int can_write;
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SuperIOConfig *superio_conf = opaque;
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2011-09-13 04:33:01 +08:00
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DPRINTF("superio_ioport_writeb address 0x%x val 0x%x\n", addr, data);
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2010-06-29 10:49:29 +08:00
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if (addr == 0x3f0) {
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superio_conf->index = data & 0xff;
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} else {
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/* 0x3f1 */
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switch (superio_conf->index) {
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case 0x00 ... 0xdf:
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case 0xe4:
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case 0xe5:
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case 0xe9 ... 0xed:
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case 0xf3:
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case 0xf5:
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case 0xf7:
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case 0xf9 ... 0xfb:
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case 0xfd ... 0xff:
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can_write = 0;
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break;
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default:
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can_write = 1;
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if (can_write) {
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switch (superio_conf->index) {
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case 0xe7:
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if ((data & 0xff) != 0xfe) {
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2011-09-13 04:33:01 +08:00
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DPRINTF("chage uart 1 base. unsupported yet\n");
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2010-06-29 10:49:29 +08:00
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}
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break;
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case 0xe8:
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if ((data & 0xff) != 0xbe) {
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2011-09-13 04:33:01 +08:00
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DPRINTF("chage uart 2 base. unsupported yet\n");
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2010-06-29 10:49:29 +08:00
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}
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break;
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default:
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superio_conf->config[superio_conf->index] = data & 0xff;
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}
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}
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}
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superio_conf->config[superio_conf->index] = data & 0xff;
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}
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}
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2013-06-22 14:06:59 +08:00
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static uint64_t superio_ioport_readb(void *opaque, hwaddr addr, unsigned size)
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2010-06-29 10:49:29 +08:00
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{
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SuperIOConfig *superio_conf = opaque;
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2011-09-13 04:33:01 +08:00
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DPRINTF("superio_ioport_readb address 0x%x\n", addr);
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2010-06-29 10:49:29 +08:00
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return (superio_conf->config[superio_conf->index]);
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}
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2013-06-22 14:06:59 +08:00
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static const MemoryRegionOps superio_ops = {
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.read = superio_ioport_readb,
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.write = superio_ioport_writeb,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.impl = {
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.min_access_size = 1,
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.max_access_size = 1,
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},
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};
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2010-06-29 10:49:29 +08:00
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static void vt82c686b_reset(void * opaque)
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{
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PCIDevice *d = opaque;
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uint8_t *pci_conf = d->config;
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VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);
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pci_set_long(pci_conf + PCI_CAPABILITY_LIST, 0x000000c0);
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pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_IO | PCI_COMMAND_MEMORY |
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PCI_COMMAND_MASTER | PCI_COMMAND_SPECIAL);
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
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pci_conf[0x48] = 0x01; /* Miscellaneous Control 3 */
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pci_conf[0x4a] = 0x04; /* IDE interrupt Routing */
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pci_conf[0x4f] = 0x03; /* DMA/Master Mem Access Control 3 */
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pci_conf[0x50] = 0x2d; /* PnP DMA Request Control */
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pci_conf[0x59] = 0x04;
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pci_conf[0x5a] = 0x04; /* KBC/RTC Control*/
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pci_conf[0x5f] = 0x04;
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pci_conf[0x77] = 0x10; /* GPIO Control 1/2/3/4 */
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vt82c->superio_conf.config[0xe0] = 0x3c;
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vt82c->superio_conf.config[0xe2] = 0x03;
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vt82c->superio_conf.config[0xe3] = 0xfc;
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vt82c->superio_conf.config[0xe6] = 0xde;
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vt82c->superio_conf.config[0xe7] = 0xfe;
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vt82c->superio_conf.config[0xe8] = 0xbe;
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}
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/* write config pci function0 registers. PCI-ISA bridge */
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static void vt82c686b_write_config(PCIDevice * d, uint32_t address,
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uint32_t val, int len)
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{
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VT82C686BState *vt686 = DO_UPCAST(VT82C686BState, dev, d);
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2011-09-13 04:33:01 +08:00
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DPRINTF("vt82c686b_write_config address 0x%x val 0x%x len 0x%x\n",
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2010-06-29 10:49:29 +08:00
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address, val, len);
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pci_default_write_config(d, address, val, len);
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if (address == 0x85) { /* enable or disable super IO configure */
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2013-06-22 14:06:59 +08:00
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memory_region_set_enabled(&vt686->superio, val & 0x2);
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2010-06-29 10:49:29 +08:00
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}
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}
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#define ACPI_DBG_IO_ADDR 0xb044
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typedef struct VT686PMState {
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PCIDevice dev;
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2012-11-23 15:29:27 +08:00
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MemoryRegion io;
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2012-02-23 20:45:16 +08:00
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ACPIREGS ar;
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2010-06-29 10:49:29 +08:00
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APMState apm;
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PMSMBus smb;
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uint32_t smb_io_base;
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} VT686PMState;
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typedef struct VT686AC97State {
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PCIDevice dev;
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} VT686AC97State;
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typedef struct VT686MC97State {
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PCIDevice dev;
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} VT686MC97State;
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static void pm_update_sci(VT686PMState *s)
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{
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int sci_level, pmsts;
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2012-02-23 20:45:17 +08:00
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pmsts = acpi_pm1_evt_get_sts(&s->ar);
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2012-02-23 20:45:16 +08:00
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sci_level = (((pmsts & s->ar.pm1.evt.en) &
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2011-03-25 18:54:39 +08:00
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(ACPI_BITMASK_RT_CLOCK_ENABLE |
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ACPI_BITMASK_POWER_BUTTON_ENABLE |
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ACPI_BITMASK_GLOBAL_LOCK_ENABLE |
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ACPI_BITMASK_TIMER_ENABLE)) != 0);
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2010-06-29 10:49:29 +08:00
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qemu_set_irq(s->dev.irq[0], sci_level);
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/* schedule a timer interruption if needed */
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2012-02-23 20:45:16 +08:00
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acpi_pm_tmr_update(&s->ar, (s->ar.pm1.evt.en & ACPI_BITMASK_TIMER_ENABLE) &&
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2011-03-25 18:54:38 +08:00
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!(pmsts & ACPI_BITMASK_TIMER_STATUS));
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2010-06-29 10:49:29 +08:00
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}
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2012-02-23 20:45:16 +08:00
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static void pm_tmr_timer(ACPIREGS *ar)
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2010-06-29 10:49:29 +08:00
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{
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2012-02-23 20:45:16 +08:00
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VT686PMState *s = container_of(ar, VT686PMState, ar);
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2010-06-29 10:49:29 +08:00
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pm_update_sci(s);
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}
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static void pm_io_space_update(VT686PMState *s)
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{
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uint32_t pm_io_base;
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2012-11-23 15:29:27 +08:00
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pm_io_base = pci_get_long(s->dev.config + 0x40);
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pm_io_base &= 0xffc0;
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2010-06-29 10:49:29 +08:00
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2012-11-23 15:29:27 +08:00
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memory_region_transaction_begin();
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memory_region_set_enabled(&s->io, s->dev.config[0x80] & 1);
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memory_region_set_address(&s->io, pm_io_base);
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memory_region_transaction_commit();
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2010-06-29 10:49:29 +08:00
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}
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static void pm_write_config(PCIDevice *d,
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uint32_t address, uint32_t val, int len)
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{
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2011-09-13 04:33:01 +08:00
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DPRINTF("pm_write_config address 0x%x val 0x%x len 0x%x\n",
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2010-06-29 10:49:29 +08:00
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address, val, len);
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pci_default_write_config(d, address, val, len);
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}
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static int vmstate_acpi_post_load(void *opaque, int version_id)
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{
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VT686PMState *s = opaque;
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pm_io_space_update(s);
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return 0;
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}
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static const VMStateDescription vmstate_acpi = {
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.name = "vt82c686b_pm",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.post_load = vmstate_acpi_post_load,
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.fields = (VMStateField []) {
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VMSTATE_PCI_DEVICE(dev, VT686PMState),
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2012-02-23 20:45:16 +08:00
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VMSTATE_UINT16(ar.pm1.evt.sts, VT686PMState),
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VMSTATE_UINT16(ar.pm1.evt.en, VT686PMState),
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VMSTATE_UINT16(ar.pm1.cnt.cnt, VT686PMState),
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2010-06-29 10:49:29 +08:00
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VMSTATE_STRUCT(apm, VT686PMState, 0, vmstate_apm, APMState),
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2012-02-23 20:45:16 +08:00
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VMSTATE_TIMER(ar.tmr.timer, VT686PMState),
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VMSTATE_INT64(ar.tmr.overflow_time, VT686PMState),
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2010-06-29 10:49:29 +08:00
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VMSTATE_END_OF_LIST()
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}
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};
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/*
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* TODO: vt82c686b_ac97_init() and vt82c686b_mc97_init()
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* just register a PCI device now, functionalities will be implemented later.
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*/
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static int vt82c686b_ac97_initfn(PCIDevice *dev)
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{
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VT686AC97State *s = DO_UPCAST(VT686AC97State, dev, dev);
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uint8_t *pci_conf = s->dev.config;
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pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
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PCI_COMMAND_PARITY);
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_CAP_LIST |
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PCI_STATUS_DEVSEL_MEDIUM);
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pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
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return 0;
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}
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void vt82c686b_ac97_init(PCIBus *bus, int devfn)
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{
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PCIDevice *dev;
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dev = pci_create(bus, devfn, "VT82C686B_AC97");
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qdev_init_nofail(&dev->qdev);
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}
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2011-12-05 02:22:06 +08:00
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static void via_ac97_class_init(ObjectClass *klass, void *data)
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{
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2011-12-08 11:34:16 +08:00
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DeviceClass *dc = DEVICE_CLASS(klass);
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2011-12-05 02:22:06 +08:00
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PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
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k->init = vt82c686b_ac97_initfn;
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k->vendor_id = PCI_VENDOR_ID_VIA;
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k->device_id = PCI_DEVICE_ID_VIA_AC97;
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k->revision = 0x50;
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k->class_id = PCI_CLASS_MULTIMEDIA_AUDIO;
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2011-12-08 11:34:16 +08:00
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dc->desc = "AC97";
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2011-12-05 02:22:06 +08:00
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}
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2013-01-10 23:19:07 +08:00
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static const TypeInfo via_ac97_info = {
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2011-12-08 11:34:16 +08:00
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.name = "VT82C686B_AC97",
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.parent = TYPE_PCI_DEVICE,
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.instance_size = sizeof(VT686AC97State),
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.class_init = via_ac97_class_init,
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2010-06-29 10:49:29 +08:00
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};
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static int vt82c686b_mc97_initfn(PCIDevice *dev)
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{
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VT686MC97State *s = DO_UPCAST(VT686MC97State, dev, dev);
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uint8_t *pci_conf = s->dev.config;
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pci_set_word(pci_conf + PCI_COMMAND, PCI_COMMAND_INVALIDATE |
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PCI_COMMAND_VGA_PALETTE);
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pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_DEVSEL_MEDIUM);
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pci_set_long(pci_conf + PCI_INTERRUPT_PIN, 0x03);
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return 0;
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}
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|
|
|
|
|
void vt82c686b_mc97_init(PCIBus *bus, int devfn)
|
|
|
|
{
|
|
|
|
PCIDevice *dev;
|
|
|
|
|
|
|
|
dev = pci_create(bus, devfn, "VT82C686B_MC97");
|
|
|
|
qdev_init_nofail(&dev->qdev);
|
|
|
|
}
|
|
|
|
|
2011-12-05 02:22:06 +08:00
|
|
|
static void via_mc97_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 11:34:16 +08:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2011-12-05 02:22:06 +08:00
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
k->init = vt82c686b_mc97_initfn;
|
|
|
|
k->vendor_id = PCI_VENDOR_ID_VIA;
|
|
|
|
k->device_id = PCI_DEVICE_ID_VIA_MC97;
|
|
|
|
k->class_id = PCI_CLASS_COMMUNICATION_OTHER;
|
|
|
|
k->revision = 0x30;
|
2011-12-08 11:34:16 +08:00
|
|
|
dc->desc = "MC97";
|
2011-12-05 02:22:06 +08:00
|
|
|
}
|
|
|
|
|
2013-01-10 23:19:07 +08:00
|
|
|
static const TypeInfo via_mc97_info = {
|
2011-12-08 11:34:16 +08:00
|
|
|
.name = "VT82C686B_MC97",
|
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(VT686MC97State),
|
|
|
|
.class_init = via_mc97_class_init,
|
2010-06-29 10:49:29 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
/* vt82c686 pm init */
|
|
|
|
static int vt82c686b_pm_initfn(PCIDevice *dev)
|
|
|
|
{
|
|
|
|
VT686PMState *s = DO_UPCAST(VT686PMState, dev, dev);
|
|
|
|
uint8_t *pci_conf;
|
|
|
|
|
|
|
|
pci_conf = s->dev.config;
|
|
|
|
pci_set_word(pci_conf + PCI_COMMAND, 0);
|
|
|
|
pci_set_word(pci_conf + PCI_STATUS, PCI_STATUS_FAST_BACK |
|
|
|
|
PCI_STATUS_DEVSEL_MEDIUM);
|
|
|
|
|
|
|
|
/* 0x48-0x4B is Power Management I/O Base */
|
|
|
|
pci_set_long(pci_conf + 0x48, 0x00000001);
|
|
|
|
|
|
|
|
/* SMB ports:0xeee0~0xeeef */
|
|
|
|
s->smb_io_base =((s->smb_io_base & 0xfff0) + 0x0);
|
|
|
|
pci_conf[0x90] = s->smb_io_base | 1;
|
|
|
|
pci_conf[0x91] = s->smb_io_base >> 8;
|
|
|
|
pci_conf[0xd2] = 0x90;
|
2012-11-23 21:57:01 +08:00
|
|
|
pm_smbus_init(&s->dev.qdev, &s->smb);
|
|
|
|
memory_region_add_subregion(get_system_io(), s->smb_io_base, &s->smb.io);
|
2010-06-29 10:49:29 +08:00
|
|
|
|
2012-09-19 19:50:03 +08:00
|
|
|
apm_init(dev, &s->apm, NULL, s);
|
2010-06-29 10:49:29 +08:00
|
|
|
|
2013-06-06 17:41:28 +08:00
|
|
|
memory_region_init(&s->io, NULL, "vt82c686-pm", 64);
|
2012-11-23 15:29:27 +08:00
|
|
|
memory_region_set_enabled(&s->io, false);
|
|
|
|
memory_region_add_subregion(get_system_io(), 0, &s->io);
|
2010-06-29 10:49:29 +08:00
|
|
|
|
2012-11-22 19:12:30 +08:00
|
|
|
acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io);
|
2012-11-22 20:25:10 +08:00
|
|
|
acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io);
|
2013-04-03 02:41:40 +08:00
|
|
|
acpi_pm1_cnt_init(&s->ar, &s->io, 2);
|
2010-06-29 10:49:29 +08:00
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
i2c_bus *vt82c686b_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
|
|
|
|
qemu_irq sci_irq)
|
|
|
|
{
|
|
|
|
PCIDevice *dev;
|
|
|
|
VT686PMState *s;
|
|
|
|
|
|
|
|
dev = pci_create(bus, devfn, "VT82C686B_PM");
|
|
|
|
qdev_prop_set_uint32(&dev->qdev, "smb_io_base", smb_io_base);
|
|
|
|
|
|
|
|
s = DO_UPCAST(VT686PMState, dev, dev);
|
|
|
|
|
|
|
|
qdev_init_nofail(&dev->qdev);
|
|
|
|
|
|
|
|
return s->smb.smbus;
|
|
|
|
}
|
|
|
|
|
2011-12-05 02:22:06 +08:00
|
|
|
static Property via_pm_properties[] = {
|
|
|
|
DEFINE_PROP_UINT32("smb_io_base", VT686PMState, smb_io_base, 0),
|
|
|
|
DEFINE_PROP_END_OF_LIST(),
|
|
|
|
};
|
|
|
|
|
|
|
|
static void via_pm_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 11:34:16 +08:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2011-12-05 02:22:06 +08:00
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
k->init = vt82c686b_pm_initfn;
|
|
|
|
k->config_write = pm_write_config;
|
|
|
|
k->vendor_id = PCI_VENDOR_ID_VIA;
|
|
|
|
k->device_id = PCI_DEVICE_ID_VIA_ACPI;
|
|
|
|
k->class_id = PCI_CLASS_BRIDGE_OTHER;
|
|
|
|
k->revision = 0x40;
|
2011-12-08 11:34:16 +08:00
|
|
|
dc->desc = "PM";
|
|
|
|
dc->vmsd = &vmstate_acpi;
|
|
|
|
dc->props = via_pm_properties;
|
2011-12-05 02:22:06 +08:00
|
|
|
}
|
|
|
|
|
2013-01-10 23:19:07 +08:00
|
|
|
static const TypeInfo via_pm_info = {
|
2011-12-08 11:34:16 +08:00
|
|
|
.name = "VT82C686B_PM",
|
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(VT686PMState),
|
|
|
|
.class_init = via_pm_class_init,
|
2010-06-29 10:49:29 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
static const VMStateDescription vmstate_via = {
|
|
|
|
.name = "vt82c686b",
|
|
|
|
.version_id = 1,
|
|
|
|
.minimum_version_id = 1,
|
|
|
|
.minimum_version_id_old = 1,
|
|
|
|
.fields = (VMStateField []) {
|
|
|
|
VMSTATE_PCI_DEVICE(dev, VT82C686BState),
|
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
/* init the PCI-to-ISA bridge */
|
|
|
|
static int vt82c686b_initfn(PCIDevice *d)
|
|
|
|
{
|
2013-06-22 14:06:59 +08:00
|
|
|
VT82C686BState *vt82c = DO_UPCAST(VT82C686BState, dev, d);
|
2010-06-29 10:49:29 +08:00
|
|
|
uint8_t *pci_conf;
|
2013-06-22 14:06:59 +08:00
|
|
|
ISABus *isa_bus;
|
2010-06-29 10:49:29 +08:00
|
|
|
uint8_t *wmask;
|
|
|
|
int i;
|
|
|
|
|
2013-06-22 14:06:59 +08:00
|
|
|
isa_bus = isa_bus_new(&d->qdev, pci_address_space_io(d));
|
2010-06-29 10:49:29 +08:00
|
|
|
|
|
|
|
pci_conf = d->config;
|
|
|
|
pci_config_set_prog_interface(pci_conf, 0x0);
|
|
|
|
|
|
|
|
wmask = d->wmask;
|
|
|
|
for (i = 0x00; i < 0xff; i++) {
|
|
|
|
if (i<=0x03 || (i>=0x08 && i<=0x3f)) {
|
|
|
|
wmask[i] = 0x00;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2013-06-07 09:19:53 +08:00
|
|
|
memory_region_init_io(&vt82c->superio, OBJECT(d), &superio_ops,
|
2013-06-06 17:41:28 +08:00
|
|
|
&vt82c->superio_conf, "superio", 2);
|
2013-06-22 14:06:59 +08:00
|
|
|
memory_region_set_enabled(&vt82c->superio, false);
|
|
|
|
/* The floppy also uses 0x3f0 and 0x3f1.
|
|
|
|
* But we do not emulate a floppy, so just set it here. */
|
|
|
|
memory_region_add_subregion(isa_bus->address_space_io, 0x3f0,
|
|
|
|
&vt82c->superio);
|
|
|
|
|
2010-06-29 10:49:29 +08:00
|
|
|
qemu_register_reset(vt82c686b_reset, d);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2011-12-16 05:09:57 +08:00
|
|
|
ISABus *vt82c686b_init(PCIBus *bus, int devfn)
|
2010-06-29 10:49:29 +08:00
|
|
|
{
|
|
|
|
PCIDevice *d;
|
|
|
|
|
2010-07-12 19:53:57 +08:00
|
|
|
d = pci_create_simple_multifunction(bus, devfn, true, "VT82C686B");
|
2010-06-29 10:49:29 +08:00
|
|
|
|
2013-06-07 20:11:07 +08:00
|
|
|
return ISA_BUS(qdev_get_child_bus(DEVICE(d), "isa.0"));
|
2010-06-29 10:49:29 +08:00
|
|
|
}
|
|
|
|
|
2011-12-05 02:22:06 +08:00
|
|
|
static void via_class_init(ObjectClass *klass, void *data)
|
|
|
|
{
|
2011-12-08 11:34:16 +08:00
|
|
|
DeviceClass *dc = DEVICE_CLASS(klass);
|
2011-12-05 02:22:06 +08:00
|
|
|
PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
|
|
|
|
|
|
|
|
k->init = vt82c686b_initfn;
|
|
|
|
k->config_write = vt82c686b_write_config;
|
|
|
|
k->vendor_id = PCI_VENDOR_ID_VIA;
|
|
|
|
k->device_id = PCI_DEVICE_ID_VIA_ISA_BRIDGE;
|
|
|
|
k->class_id = PCI_CLASS_BRIDGE_ISA;
|
|
|
|
k->revision = 0x40;
|
2011-12-08 11:34:16 +08:00
|
|
|
dc->desc = "ISA bridge";
|
|
|
|
dc->no_user = 1;
|
|
|
|
dc->vmsd = &vmstate_via;
|
2011-12-05 02:22:06 +08:00
|
|
|
}
|
|
|
|
|
2013-01-10 23:19:07 +08:00
|
|
|
static const TypeInfo via_info = {
|
2011-12-08 11:34:16 +08:00
|
|
|
.name = "VT82C686B",
|
|
|
|
.parent = TYPE_PCI_DEVICE,
|
|
|
|
.instance_size = sizeof(VT82C686BState),
|
|
|
|
.class_init = via_class_init,
|
2010-06-29 10:49:29 +08:00
|
|
|
};
|
|
|
|
|
2012-02-09 22:20:55 +08:00
|
|
|
static void vt82c686b_register_types(void)
|
2010-06-29 10:49:29 +08:00
|
|
|
{
|
2012-02-09 22:20:55 +08:00
|
|
|
type_register_static(&via_ac97_info);
|
|
|
|
type_register_static(&via_mc97_info);
|
|
|
|
type_register_static(&via_pm_info);
|
2011-12-08 11:34:16 +08:00
|
|
|
type_register_static(&via_info);
|
2010-06-29 10:49:29 +08:00
|
|
|
}
|
2012-02-09 22:20:55 +08:00
|
|
|
|
|
|
|
type_init(vt82c686b_register_types)
|