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target-mips: Status.UX/SX/KX enable 32-bit address wrapping 

In R6 the special behaviour for data references is also specified for Kernel
and Supervisor mode. Therefore MIPS_HFLAG_UX is replaced by generic
MIPS_HFLAG_AWRAP indicating enabled 32-bit address wrapping.

Signed-off-by: Leon Alrae <leon.alrae@imgtec.com>
Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Leon Alrae 2014-06-27 08:49:04 +01:00
parent 4267d3e6e0
commit 01f7288579
2 changed files with 15 additions and 9 deletions
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18
target-mips/cpu.h
View File

@ -450,7 +450,7 @@ struct CPUMIPSState {
and RSQRT.D. */ and RSQRT.D. */
#define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */ #define MIPS_HFLAG_COP1X 0x00080 /* COP1X instructions enabled */
#define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */ #define MIPS_HFLAG_RE 0x00100 /* Reversed endianness */
#define MIPS_HFLAG_UX 0x00200 /* 64-bit user mode */ #define MIPS_HFLAG_AWRAP 0x00200 /* 32-bit compatibility address wrapping */
#define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */ #define MIPS_HFLAG_M16 0x00400 /* MIPS16 mode flag */
#define MIPS_HFLAG_M16_SHIFT 10 #define MIPS_HFLAG_M16_SHIFT 10
/* If translation is interrupted between the branch instruction and /* If translation is interrupted between the branch instruction and
@ -725,7 +725,7 @@ static inline void compute_hflags(CPUMIPSState *env)
{ {
env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 | env->hflags &= ~(MIPS_HFLAG_COP1X | MIPS_HFLAG_64 | MIPS_HFLAG_CP0 |
MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU | MIPS_HFLAG_F64 | MIPS_HFLAG_FPU | MIPS_HFLAG_KSU |
MIPS_HFLAG_UX | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2); MIPS_HFLAG_AWRAP | MIPS_HFLAG_DSP | MIPS_HFLAG_DSPR2);
if (!(env->CP0_Status & (1 << CP0St_EXL)) && if (!(env->CP0_Status & (1 << CP0St_EXL)) &&
!(env->CP0_Status & (1 << CP0St_ERL)) && !(env->CP0_Status & (1 << CP0St_ERL)) &&
!(env->hflags & MIPS_HFLAG_DM)) { !(env->hflags & MIPS_HFLAG_DM)) {
@ -737,8 +737,18 @@ static inline void compute_hflags(CPUMIPSState *env)
(env->CP0_Status & (1 << CP0St_UX))) { (env->CP0_Status & (1 << CP0St_UX))) {
env->hflags |= MIPS_HFLAG_64; env->hflags |= MIPS_HFLAG_64;
} }
if (env->CP0_Status & (1 << CP0St_UX)) {
env->hflags |= MIPS_HFLAG_UX; if (((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
!(env->CP0_Status & (1 << CP0St_UX))) {
env->hflags |= MIPS_HFLAG_AWRAP;
} else if (env->insn_flags & ISA_MIPS32R6) {
/* Address wrapping for Supervisor and Kernel is specified in R6 */
if ((((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_SM) &&
!(env->CP0_Status & (1 << CP0St_SX))) ||
(((env->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_KM) &&
!(env->CP0_Status & (1 << CP0St_KX)))) {
env->hflags |= MIPS_HFLAG_AWRAP;
}
} }
#endif #endif
if ((env->CP0_Status & (1 << CP0St_CU0)) || if ((env->CP0_Status & (1 << CP0St_CU0)) ||

6
target-mips/translate.c
View File

@ -1383,11 +1383,7 @@ static inline void gen_op_addr_add (DisasContext *ctx, TCGv ret, TCGv arg0, TCGv
tcg_gen_add_tl(ret, arg0, arg1); tcg_gen_add_tl(ret, arg0, arg1);
#if defined(TARGET_MIPS64) #if defined(TARGET_MIPS64)
/* For compatibility with 32-bit code, data reference in user mode if (ctx->hflags & MIPS_HFLAG_AWRAP) {
with Status_UX = 0 should be casted to 32-bit and sign extended.
See the MIPS64 PRA manual, section 4.10. */
if (((ctx->hflags & MIPS_HFLAG_KSU) == MIPS_HFLAG_UM) &&
!(ctx->hflags & MIPS_HFLAG_UX)) {
tcg_gen_ext32s_i64(ret, ret); tcg_gen_ext32s_i64(ret, ret);
} }
#endif #endif