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xlnx-zynqmp: Connect the SPI devices 

Connect the Xilinx SPI devices to the ZynqMP model.

Signed-off-by: Alistair Francis <alistair.francis@xilinx.com>
Reviewed-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
[ PC changes
 * Use QOM alias for bus connectivity on SoC level
]
Signed-off-by: Peter Crosthwaite <crosthwaite.peter@gmail.com>
[PMM: free the g_strdup_printf() string when finished with it]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alistair Francis 2016-01-21 14:15:03 +00:00 committed by Peter Maydell
parent 6363235b2b
commit 02d07eb494
2 changed files with 34 additions and 0 deletions
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31
hw/arm/xlnx-zynqmp.c
View File

@ -57,6 +57,14 @@ static const int sdhci_intr[XLNX_ZYNQMP_NUM_SDHCI] = {
48, 49, 48, 49,
}; };
static const uint64_t spi_addr[XLNX_ZYNQMP_NUM_SPIS] = {
0xFF040000, 0xFF050000,
};
static const int spi_intr[XLNX_ZYNQMP_NUM_SPIS] = {
19, 20,
};
typedef struct XlnxZynqMPGICRegion { typedef struct XlnxZynqMPGICRegion {
int region_index; int region_index;
uint32_t address; uint32_t address;
@ -118,6 +126,12 @@ static void xlnx_zynqmp_init(Object *obj)
qdev_set_parent_bus(DEVICE(&s->sdhci[i]), qdev_set_parent_bus(DEVICE(&s->sdhci[i]),
sysbus_get_default()); sysbus_get_default());
} }
for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
object_initialize(&s->spi[i], sizeof(s->spi[i]),
TYPE_XILINX_SPIPS);
qdev_set_parent_bus(DEVICE(&s->spi[i]), sysbus_get_default());
}
} }
static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
@ -324,6 +338,23 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0, sysbus_connect_irq(SYS_BUS_DEVICE(&s->sdhci[i]), 0,
gic_spi[sdhci_intr[i]]); gic_spi[sdhci_intr[i]]);
} }
for (i = 0; i < XLNX_ZYNQMP_NUM_SPIS; i++) {
gchar *bus_name;
object_property_set_bool(OBJECT(&s->spi[i]), true, "realized", &err);
sysbus_mmio_map(SYS_BUS_DEVICE(&s->spi[i]), 0, spi_addr[i]);
sysbus_connect_irq(SYS_BUS_DEVICE(&s->spi[i]), 0,
gic_spi[spi_intr[i]]);
/* Alias controller SPI bus to the SoC itself */
bus_name = g_strdup_printf("spi%d", i);
object_property_add_alias(OBJECT(s), bus_name,
OBJECT(&s->spi[i]), "spi0",
&error_abort);
g_free(bus_name);
}
} }
static Property xlnx_zynqmp_props[] = { static Property xlnx_zynqmp_props[] = {

3
include/hw/arm/xlnx-zynqmp.h
View File

@ -25,6 +25,7 @@
#include "hw/ide/pci.h" #include "hw/ide/pci.h"
#include "hw/ide/ahci.h" #include "hw/ide/ahci.h"
#include "hw/sd/sdhci.h" #include "hw/sd/sdhci.h"
#include "hw/ssi/xilinx_spips.h"
#define TYPE_XLNX_ZYNQMP "xlnx,zynqmp" #define TYPE_XLNX_ZYNQMP "xlnx,zynqmp"
#define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \ #define XLNX_ZYNQMP(obj) OBJECT_CHECK(XlnxZynqMPState, (obj), \
@ -35,6 +36,7 @@
#define XLNX_ZYNQMP_NUM_GEMS 4 #define XLNX_ZYNQMP_NUM_GEMS 4
#define XLNX_ZYNQMP_NUM_UARTS 2 #define XLNX_ZYNQMP_NUM_UARTS 2
#define XLNX_ZYNQMP_NUM_SDHCI 2 #define XLNX_ZYNQMP_NUM_SDHCI 2
#define XLNX_ZYNQMP_NUM_SPIS 2
#define XLNX_ZYNQMP_NUM_OCM_BANKS 4 #define XLNX_ZYNQMP_NUM_OCM_BANKS 4
#define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000 #define XLNX_ZYNQMP_OCM_RAM_0_ADDRESS 0xFFFC0000
@ -78,6 +80,7 @@ typedef struct XlnxZynqMPState {
CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS]; CadenceUARTState uart[XLNX_ZYNQMP_NUM_UARTS];
SysbusAHCIState sata; SysbusAHCIState sata;
SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI]; SDHCIState sdhci[XLNX_ZYNQMP_NUM_SDHCI];
XilinxSPIPS spi[XLNX_ZYNQMP_NUM_SPIS];
char *boot_cpu; char *boot_cpu;
ARMCPU *boot_cpu_ptr; ARMCPU *boot_cpu_ptr;