mirror of https://gitee.com/openkylin/qemu.git
qemu/pci: MSI-X support functions
Add functions implementing MSI-X support. First user will be virtio-pci. Note that platform must set a flag to declare MSI supported: this is a safety measure to avoid breaking platforms which should support MSI-X but currently lack this in the interrupt controller emulation. For PC this will be set by APIC. Signed-off-by: Michael S. Tsirkin <mst@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Michael S. Tsirkin
Anthony Liguori
parent
bd4b65ee5e
commit
02eb84d0ec
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@ -495,7 +495,7 @@ endif #CONFIG_BSD_USER
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ifndef CONFIG_USER_ONLY
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OBJS=vl.o osdep.o monitor.o pci.o loader.o isa_mmio.o machine.o \
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gdbstub.o gdbstub-xml.o
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gdbstub.o gdbstub-xml.o msix.o
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# virtio has to be here due to weird dependency between PCI and virtio-net.
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# need to fix this properly
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OBJS+=virtio-blk.o virtio-balloon.o virtio-net.o virtio-console.o
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@ -0,0 +1,378 @@
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/*
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* MSI-X device support
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*
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* This module includes support for MSI-X in pci devices.
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*
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* Author: Michael S. Tsirkin <mst@redhat.com>
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*
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* Copyright (c) 2009, Red Hat Inc, Michael S. Tsirkin (mst@redhat.com)
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*
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* This work is licensed under the terms of the GNU GPL, version 2. See
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* the COPYING file in the top-level directory.
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*/
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#include "hw.h"
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#include "msix.h"
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#include "pci.h"
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/* Declaration from linux/pci_regs.h */
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#define PCI_CAP_ID_MSIX 0x11 /* MSI-X */
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#define PCI_MSIX_FLAGS 2 /* Table at lower 11 bits */
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#define PCI_MSIX_FLAGS_QSIZE 0x7FF
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#define PCI_MSIX_FLAGS_ENABLE (1 << 15)
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#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
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/* MSI-X capability structure */
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#define MSIX_TABLE_OFFSET 4
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#define MSIX_PBA_OFFSET 8
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#define MSIX_CAP_LENGTH 12
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/* MSI enable bit is in byte 1 in FLAGS register */
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#define MSIX_ENABLE_OFFSET (PCI_MSIX_FLAGS + 1)
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#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
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/* MSI-X table format */
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#define MSIX_MSG_ADDR 0
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#define MSIX_MSG_UPPER_ADDR 4
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#define MSIX_MSG_DATA 8
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#define MSIX_VECTOR_CTRL 12
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#define MSIX_ENTRY_SIZE 16
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#define MSIX_VECTOR_MASK 0x1
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/* How much space does an MSIX table need. */
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/* The spec requires giving the table structure
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* a 4K aligned region all by itself. Align it to
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* target pages so that drivers can do passthrough
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* on the rest of the region. */
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#define MSIX_PAGE_SIZE TARGET_PAGE_ALIGN(0x1000)
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/* Reserve second half of the page for pending bits */
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#define MSIX_PAGE_PENDING (MSIX_PAGE_SIZE / 2)
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#define MSIX_MAX_ENTRIES 32
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#ifdef MSIX_DEBUG
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#define DEBUG(fmt, ...) \
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do { \
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fprintf(stderr, "%s: " fmt, __func__ , __VA_ARGS__); \
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} while (0)
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#else
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#define DEBUG(fmt, ...) do { } while(0)
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#endif
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/* Flag for interrupt controller to declare MSI-X support */
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int msix_supported;
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/* Add MSI-X capability to the config space for the device. */
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/* Given a bar and its size, add MSI-X table on top of it
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* and fill MSI-X capability in the config space.
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* Original bar size must be a power of 2 or 0.
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* New bar size is returned. */
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static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
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unsigned bar_nr, unsigned bar_size)
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{
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int config_offset;
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uint8_t *config;
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uint32_t new_size;
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if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
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return -EINVAL;
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if (bar_size > 0x80000000)
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return -ENOSPC;
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/* Add space for MSI-X structures */
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if (!bar_size)
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new_size = MSIX_PAGE_SIZE;
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else if (bar_size < MSIX_PAGE_SIZE) {
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bar_size = MSIX_PAGE_SIZE;
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new_size = MSIX_PAGE_SIZE * 2;
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} else
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new_size = bar_size * 2;
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pdev->msix_bar_size = new_size;
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config_offset = pci_add_capability(pdev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
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if (config_offset < 0)
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return config_offset;
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config = pdev->config + config_offset;
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pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
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/* Table on top of BAR */
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pci_set_long(config + MSIX_TABLE_OFFSET, bar_size | bar_nr);
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/* Pending bits on top of that */
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pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + MSIX_PAGE_PENDING) |
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bar_nr);
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pdev->msix_cap = config_offset;
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/* Make flags bit writeable. */
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pdev->wmask[config_offset + MSIX_ENABLE_OFFSET] |= MSIX_ENABLE_MASK;
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return 0;
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}
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static void msix_free_irq_entries(PCIDevice *dev)
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{
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int vector;
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for (vector = 0; vector < dev->msix_entries_nr; ++vector)
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dev->msix_entry_used[vector] = 0;
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}
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/* Handle MSI-X capability config write. */
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void msix_write_config(PCIDevice *dev, uint32_t addr,
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uint32_t val, int len)
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{
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unsigned enable_pos = dev->msix_cap + MSIX_ENABLE_OFFSET;
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if (addr + len <= enable_pos || addr > enable_pos)
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return;
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if (msix_enabled(dev))
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qemu_set_irq(dev->irq[0], 0);
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}
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static uint32_t msix_mmio_readl(void *opaque, target_phys_addr_t addr)
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{
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PCIDevice *dev = opaque;
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unsigned int offset = addr & (MSIX_PAGE_SIZE - 1);
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void *page = dev->msix_table_page;
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uint32_t val = 0;
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memcpy(&val, (void *)((char *)page + offset), 4);
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return val;
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}
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static uint32_t msix_mmio_read_unallowed(void *opaque, target_phys_addr_t addr)
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{
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fprintf(stderr, "MSI-X: only dword read is allowed!\n");
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return 0;
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}
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static uint8_t msix_pending_mask(int vector)
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{
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return 1 << (vector % 8);
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}
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static uint8_t *msix_pending_byte(PCIDevice *dev, int vector)
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{
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return dev->msix_table_page + MSIX_PAGE_PENDING + vector / 8;
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}
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static int msix_is_pending(PCIDevice *dev, int vector)
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{
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return *msix_pending_byte(dev, vector) & msix_pending_mask(vector);
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}
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static void msix_set_pending(PCIDevice *dev, int vector)
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{
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*msix_pending_byte(dev, vector) |= msix_pending_mask(vector);
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}
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static void msix_clr_pending(PCIDevice *dev, int vector)
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{
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*msix_pending_byte(dev, vector) &= ~msix_pending_mask(vector);
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}
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static int msix_is_masked(PCIDevice *dev, int vector)
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{
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unsigned offset = vector * MSIX_ENTRY_SIZE + MSIX_VECTOR_CTRL;
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return dev->msix_table_page[offset] & MSIX_VECTOR_MASK;
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}
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static void msix_mmio_writel(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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PCIDevice *dev = opaque;
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unsigned int offset = addr & (MSIX_PAGE_SIZE - 1);
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int vector = offset / MSIX_ENTRY_SIZE;
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memcpy(dev->msix_table_page + offset, &val, 4);
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if (!msix_is_masked(dev, vector) && msix_is_pending(dev, vector)) {
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msix_clr_pending(dev, vector);
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msix_notify(dev, vector);
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}
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}
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static void msix_mmio_write_unallowed(void *opaque, target_phys_addr_t addr,
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uint32_t val)
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{
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fprintf(stderr, "MSI-X: only dword write is allowed!\n");
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}
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static CPUWriteMemoryFunc *msix_mmio_write[] = {
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msix_mmio_write_unallowed, msix_mmio_write_unallowed, msix_mmio_writel
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};
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static CPUReadMemoryFunc *msix_mmio_read[] = {
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msix_mmio_read_unallowed, msix_mmio_read_unallowed, msix_mmio_readl
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};
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/* Should be called from device's map method. */
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void msix_mmio_map(PCIDevice *d, int region_num,
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uint32_t addr, uint32_t size, int type)
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{
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uint8_t *config = d->config + d->msix_cap;
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uint32_t table = pci_get_long(config + MSIX_TABLE_OFFSET);
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uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
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/* TODO: for assigned devices, we'll want to make it possible to map
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* pending bits separately in case they are in a separate bar. */
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int table_bir = table & PCI_MSIX_FLAGS_BIRMASK;
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if (table_bir != region_num)
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return;
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if (size <= offset)
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return;
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cpu_register_physical_memory(addr + offset, size - offset,
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d->msix_mmio_index);
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}
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/* Initialize the MSI-X structures. Note: if MSI-X is supported, BAR size is
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* modified, it should be retrieved with msix_bar_size. */
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int msix_init(struct PCIDevice *dev, unsigned short nentries,
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unsigned bar_nr, unsigned bar_size)
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{
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int ret;
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/* Nothing to do if MSI is not supported by interrupt controller */
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if (!msix_supported)
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return -ENOTSUP;
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if (nentries > MSIX_MAX_ENTRIES)
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return -EINVAL;
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dev->msix_entry_used = qemu_mallocz(MSIX_MAX_ENTRIES *
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sizeof *dev->msix_entry_used);
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dev->msix_table_page = qemu_mallocz(MSIX_PAGE_SIZE);
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dev->msix_mmio_index = cpu_register_io_memory(msix_mmio_read,
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msix_mmio_write, dev);
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if (dev->msix_mmio_index == -1) {
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ret = -EBUSY;
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goto err_index;
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}
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dev->msix_entries_nr = nentries;
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ret = msix_add_config(dev, nentries, bar_nr, bar_size);
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if (ret)
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goto err_config;
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dev->cap_present |= QEMU_PCI_CAP_MSIX;
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return 0;
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err_config:
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cpu_unregister_io_memory(dev->msix_mmio_index);
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err_index:
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qemu_free(dev->msix_table_page);
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dev->msix_table_page = NULL;
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qemu_free(dev->msix_entry_used);
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dev->msix_entry_used = NULL;
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return ret;
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}
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/* Clean up resources for the device. */
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int msix_uninit(PCIDevice *dev)
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{
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if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
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return 0;
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pci_del_capability(dev, PCI_CAP_ID_MSIX, MSIX_CAP_LENGTH);
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dev->msix_cap = 0;
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msix_free_irq_entries(dev);
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dev->msix_entries_nr = 0;
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cpu_unregister_io_memory(dev->msix_mmio_index);
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qemu_free(dev->msix_table_page);
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dev->msix_table_page = NULL;
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qemu_free(dev->msix_entry_used);
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dev->msix_entry_used = NULL;
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dev->cap_present &= ~QEMU_PCI_CAP_MSIX;
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return 0;
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}
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void msix_save(PCIDevice *dev, QEMUFile *f)
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{
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unsigned nentries = (pci_get_word(dev->config + PCI_MSIX_FLAGS) &
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PCI_MSIX_FLAGS_QSIZE) + 1;
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qemu_put_buffer(f, dev->msix_table_page, nentries * MSIX_ENTRY_SIZE);
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qemu_put_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING,
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(nentries + 7) / 8);
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}
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/* Should be called after restoring the config space. */
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void msix_load(PCIDevice *dev, QEMUFile *f)
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{
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unsigned n = dev->msix_entries_nr;
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if (!dev->cap_present & QEMU_PCI_CAP_MSIX)
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return;
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qemu_get_buffer(f, dev->msix_table_page, n * MSIX_ENTRY_SIZE);
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qemu_get_buffer(f, dev->msix_table_page + MSIX_PAGE_PENDING, (n + 7) / 8);
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}
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/* Does device support MSI-X? */
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int msix_present(PCIDevice *dev)
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{
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return dev->cap_present & QEMU_PCI_CAP_MSIX;
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}
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/* Is MSI-X enabled? */
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int msix_enabled(PCIDevice *dev)
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{
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return (dev->cap_present & QEMU_PCI_CAP_MSIX) &&
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(dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &
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MSIX_ENABLE_MASK);
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}
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/* Size of bar where MSI-X table resides, or 0 if MSI-X not supported. */
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uint32_t msix_bar_size(PCIDevice *dev)
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{
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return (dev->cap_present & QEMU_PCI_CAP_MSIX) ?
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dev->msix_bar_size : 0;
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}
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/* Send an MSI-X message */
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void msix_notify(PCIDevice *dev, unsigned vector)
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{
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uint8_t *table_entry = dev->msix_table_page + vector * MSIX_ENTRY_SIZE;
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uint64_t address;
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uint32_t data;
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if (vector >= dev->msix_entries_nr || !dev->msix_entry_used[vector])
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return;
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if (msix_is_masked(dev, vector)) {
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msix_set_pending(dev, vector);
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return;
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}
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address = pci_get_long(table_entry + MSIX_MSG_UPPER_ADDR);
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address = (address << 32) | pci_get_long(table_entry + MSIX_MSG_ADDR);
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data = pci_get_long(table_entry + MSIX_MSG_DATA);
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stl_phys(address, data);
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}
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void msix_reset(PCIDevice *dev)
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{
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if (!(dev->cap_present & QEMU_PCI_CAP_MSIX))
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return;
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msix_free_irq_entries(dev);
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dev->config[dev->msix_cap + MSIX_ENABLE_OFFSET] &= MSIX_ENABLE_MASK;
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memset(dev->msix_table_page, 0, MSIX_PAGE_SIZE);
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}
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/* PCI spec suggests that devices make it possible for software to configure
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* less vectors than supported by the device, but does not specify a standard
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* mechanism for devices to do so.
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*
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* We support this by asking devices to declare vectors software is going to
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* actually use, and checking this on the notification path. Devices that
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* don't want to follow the spec suggestion can declare all vectors as used. */
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/* Mark vector as used. */
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int msix_vector_use(PCIDevice *dev, unsigned vector)
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{
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if (vector >= dev->msix_entries_nr)
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return -EINVAL;
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dev->msix_entry_used[vector]++;
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return 0;
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}
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/* Mark vector as unused. */
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void msix_vector_unuse(PCIDevice *dev, unsigned vector)
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{
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if (vector < dev->msix_entries_nr && dev->msix_entry_used[vector])
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--dev->msix_entry_used[vector];
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}
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@ -0,0 +1,34 @@
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#ifndef QEMU_MSIX_H
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#define QEMU_MSIX_H
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#include "qemu-common.h"
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int msix_init(PCIDevice *pdev, unsigned short nentries,
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unsigned bar_nr, unsigned bar_size);
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void msix_write_config(PCIDevice *pci_dev, uint32_t address,
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uint32_t val, int len);
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void msix_mmio_map(PCIDevice *pci_dev, int region_num,
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uint32_t addr, uint32_t size, int type);
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int msix_uninit(PCIDevice *d);
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void msix_save(PCIDevice *dev, QEMUFile *f);
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void msix_load(PCIDevice *dev, QEMUFile *f);
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int msix_enabled(PCIDevice *dev);
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int msix_present(PCIDevice *dev);
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uint32_t msix_bar_size(PCIDevice *dev);
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int msix_vector_use(PCIDevice *dev, unsigned vector);
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void msix_vector_unuse(PCIDevice *dev, unsigned vector);
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void msix_notify(PCIDevice *dev, unsigned vector);
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void msix_reset(PCIDevice *dev);
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extern int msix_supported;
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#endif
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23
hw/pci.h
23
hw/pci.h
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@ -155,6 +155,11 @@ typedef struct PCIIORegion {
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/* Size of the standard PCI config space */
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#define PCI_CONFIG_SPACE_SIZE 0x100
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/* Bits in cap_present field. */
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enum {
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QEMU_PCI_CAP_MSIX = 0x1,
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};
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struct PCIDevice {
|
||||
DeviceState qdev;
|
||||
/* PCI config space */
|
||||
|
|
@ -186,6 +191,24 @@ struct PCIDevice {
|
|||
|
||||
/* Current IRQ levels. Used internally by the generic PCI code. */
|
||||
int irq_state[4];
|
||||
|
||||
/* Capability bits */
|
||||
uint32_t cap_present;
|
||||
|
||||
/* Offset of MSI-X capability in config space */
|
||||
uint8_t msix_cap;
|
||||
|
||||
/* MSI-X entries */
|
||||
int msix_entries_nr;
|
||||
|
||||
/* Space to store MSIX table */
|
||||
uint8_t *msix_table_page;
|
||||
/* MMIO index used to map MSIX table and pending bit entries. */
|
||||
int msix_mmio_index;
|
||||
/* Reference-count for entries actually in use by driver. */
|
||||
unsigned *msix_entry_used;
|
||||
/* Region including the MSI-X table */
|
||||
uint32_t msix_bar_size;
|
||||
};
|
||||
|
||||
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
|
||||
|
|
|
|||
Loading…
Reference in New Issue