mirror of https://gitee.com/openkylin/qemu.git
target/arm: Implement SVE Integer Reduction Group
Excepting MOVPRFX, which isn't a reduction. Presumably it is placed within the group because of its encoding. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180516223007.10256-10-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
f97cfd596e
commit
047cec971d
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@ -168,6 +168,50 @@ DEF_HELPER_FLAGS_5(sve_udiv_zpzz_s, TCG_CALL_NO_RWG,
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DEF_HELPER_FLAGS_5(sve_udiv_zpzz_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_orv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_orv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_orv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_orv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_eorv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_eorv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_eorv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_eorv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_andv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_andv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_andv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_andv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_saddv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_saddv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_saddv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_uaddv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_uaddv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_uaddv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_uaddv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_smaxv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_smaxv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_smaxv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_smaxv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_umaxv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_umaxv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_umaxv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_umaxv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_sminv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_sminv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_sminv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_sminv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_uminv_b, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_uminv_h, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_uminv_s, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_3(sve_uminv_d, TCG_CALL_NO_RWG, i64, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_and_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_bic_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_eor_pppp, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, ptr, i32)
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@ -36,6 +36,7 @@
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&rr_esz rd rn esz
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&rri rd rn imm
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&rrr_esz rd rn rm esz
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&rpr_esz rd pg rn esz
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&rprr_s rd pg rn rm s
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&rprr_esz rd pg rn rm esz
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@ -61,6 +62,9 @@
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@rdm_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 \
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&rprr_esz rm=%reg_movprfx
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# One register operand, with governing predicate, vector element size
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@rd_pg_rn ........ esz:2 ... ... ... pg:3 rn:5 rd:5 &rpr_esz
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# Basic Load/Store with 9-bit immediate offset
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@pd_rn_i9 ........ ........ ...... rn:5 . rd:4 \
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&rri imm=%imm9_16_10
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@ -101,6 +105,24 @@ UDIV_zpzz 00000100 .. 010 101 000 ... ..... ..... @rdn_pg_rm
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SDIV_zpzz 00000100 .. 010 110 000 ... ..... ..... @rdm_pg_rn # SDIVR
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UDIV_zpzz 00000100 .. 010 111 000 ... ..... ..... @rdm_pg_rn # UDIVR
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### SVE Integer Reduction Group
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# SVE bitwise logical reduction (predicated)
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ORV 00000100 .. 011 000 001 ... ..... ..... @rd_pg_rn
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EORV 00000100 .. 011 001 001 ... ..... ..... @rd_pg_rn
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ANDV 00000100 .. 011 010 001 ... ..... ..... @rd_pg_rn
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# SVE integer add reduction (predicated)
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# Note that saddv requires size != 3.
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UADDV 00000100 .. 000 001 001 ... ..... ..... @rd_pg_rn
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SADDV 00000100 .. 000 000 001 ... ..... ..... @rd_pg_rn
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# SVE integer min/max reduction (predicated)
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SMAXV 00000100 .. 001 000 001 ... ..... ..... @rd_pg_rn
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UMAXV 00000100 .. 001 001 001 ... ..... ..... @rd_pg_rn
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SMINV 00000100 .. 001 010 001 ... ..... ..... @rd_pg_rn
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UMINV 00000100 .. 001 011 001 ... ..... ..... @rd_pg_rn
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### SVE Logical - Unpredicated Group
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# SVE bitwise logical operations (unpredicated)
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@ -298,6 +298,97 @@ DO_ZPZZ_D(sve_udiv_zpzz_d, uint64_t, DO_DIV)
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#undef DO_ZPZZ
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#undef DO_ZPZZ_D
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/* Two-operand reduction expander, controlled by a predicate.
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* The difference between TYPERED and TYPERET has to do with
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* sign-extension. E.g. for SMAX, TYPERED must be signed,
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* but TYPERET must be unsigned so that e.g. a 32-bit value
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* is not sign-extended to the ABI uint64_t return type.
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*/
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/* ??? If we were to vectorize this by hand the reduction ordering
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* would change. For integer operands, this is perfectly fine.
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*/
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#define DO_VPZ(NAME, TYPEELT, TYPERED, TYPERET, H, INIT, OP) \
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uint64_t HELPER(NAME)(void *vn, void *vg, uint32_t desc) \
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{ \
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intptr_t i, opr_sz = simd_oprsz(desc); \
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TYPERED ret = INIT; \
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for (i = 0; i < opr_sz; ) { \
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uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \
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do { \
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if (pg & 1) { \
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TYPEELT nn = *(TYPEELT *)(vn + H(i)); \
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ret = OP(ret, nn); \
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} \
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i += sizeof(TYPEELT), pg >>= sizeof(TYPEELT); \
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} while (i & 15); \
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} \
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return (TYPERET)ret; \
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}
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#define DO_VPZ_D(NAME, TYPEE, TYPER, INIT, OP) \
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uint64_t HELPER(NAME)(void *vn, void *vg, uint32_t desc) \
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{ \
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intptr_t i, opr_sz = simd_oprsz(desc) / 8; \
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TYPEE *n = vn; \
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uint8_t *pg = vg; \
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TYPER ret = INIT; \
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for (i = 0; i < opr_sz; i += 1) { \
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if (pg[H1(i)] & 1) { \
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TYPEE nn = n[i]; \
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ret = OP(ret, nn); \
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} \
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} \
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return ret; \
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}
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DO_VPZ(sve_orv_b, uint8_t, uint8_t, uint8_t, H1, 0, DO_ORR)
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DO_VPZ(sve_orv_h, uint16_t, uint16_t, uint16_t, H1_2, 0, DO_ORR)
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DO_VPZ(sve_orv_s, uint32_t, uint32_t, uint32_t, H1_4, 0, DO_ORR)
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DO_VPZ_D(sve_orv_d, uint64_t, uint64_t, 0, DO_ORR)
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DO_VPZ(sve_eorv_b, uint8_t, uint8_t, uint8_t, H1, 0, DO_EOR)
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DO_VPZ(sve_eorv_h, uint16_t, uint16_t, uint16_t, H1_2, 0, DO_EOR)
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DO_VPZ(sve_eorv_s, uint32_t, uint32_t, uint32_t, H1_4, 0, DO_EOR)
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DO_VPZ_D(sve_eorv_d, uint64_t, uint64_t, 0, DO_EOR)
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DO_VPZ(sve_andv_b, uint8_t, uint8_t, uint8_t, H1, -1, DO_AND)
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DO_VPZ(sve_andv_h, uint16_t, uint16_t, uint16_t, H1_2, -1, DO_AND)
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DO_VPZ(sve_andv_s, uint32_t, uint32_t, uint32_t, H1_4, -1, DO_AND)
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DO_VPZ_D(sve_andv_d, uint64_t, uint64_t, -1, DO_AND)
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DO_VPZ(sve_saddv_b, int8_t, uint64_t, uint64_t, H1, 0, DO_ADD)
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DO_VPZ(sve_saddv_h, int16_t, uint64_t, uint64_t, H1_2, 0, DO_ADD)
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DO_VPZ(sve_saddv_s, int32_t, uint64_t, uint64_t, H1_4, 0, DO_ADD)
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DO_VPZ(sve_uaddv_b, uint8_t, uint64_t, uint64_t, H1, 0, DO_ADD)
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DO_VPZ(sve_uaddv_h, uint16_t, uint64_t, uint64_t, H1_2, 0, DO_ADD)
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DO_VPZ(sve_uaddv_s, uint32_t, uint64_t, uint64_t, H1_4, 0, DO_ADD)
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DO_VPZ_D(sve_uaddv_d, uint64_t, uint64_t, 0, DO_ADD)
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DO_VPZ(sve_smaxv_b, int8_t, int8_t, uint8_t, H1, INT8_MIN, DO_MAX)
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DO_VPZ(sve_smaxv_h, int16_t, int16_t, uint16_t, H1_2, INT16_MIN, DO_MAX)
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DO_VPZ(sve_smaxv_s, int32_t, int32_t, uint32_t, H1_4, INT32_MIN, DO_MAX)
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DO_VPZ_D(sve_smaxv_d, int64_t, int64_t, INT64_MIN, DO_MAX)
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DO_VPZ(sve_umaxv_b, uint8_t, uint8_t, uint8_t, H1, 0, DO_MAX)
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DO_VPZ(sve_umaxv_h, uint16_t, uint16_t, uint16_t, H1_2, 0, DO_MAX)
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DO_VPZ(sve_umaxv_s, uint32_t, uint32_t, uint32_t, H1_4, 0, DO_MAX)
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DO_VPZ_D(sve_umaxv_d, uint64_t, uint64_t, 0, DO_MAX)
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DO_VPZ(sve_sminv_b, int8_t, int8_t, uint8_t, H1, INT8_MAX, DO_MIN)
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DO_VPZ(sve_sminv_h, int16_t, int16_t, uint16_t, H1_2, INT16_MAX, DO_MIN)
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DO_VPZ(sve_sminv_s, int32_t, int32_t, uint32_t, H1_4, INT32_MAX, DO_MIN)
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DO_VPZ_D(sve_sminv_d, int64_t, int64_t, INT64_MAX, DO_MIN)
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DO_VPZ(sve_uminv_b, uint8_t, uint8_t, uint8_t, H1, -1, DO_MIN)
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DO_VPZ(sve_uminv_h, uint16_t, uint16_t, uint16_t, H1_2, -1, DO_MIN)
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DO_VPZ(sve_uminv_s, uint32_t, uint32_t, uint32_t, H1_4, -1, DO_MIN)
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DO_VPZ_D(sve_uminv_d, uint64_t, uint64_t, -1, DO_MIN)
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#undef DO_VPZ
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#undef DO_VPZ_D
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#undef DO_AND
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#undef DO_ORR
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#undef DO_EOR
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@ -295,6 +295,74 @@ static bool trans_UDIV_zpzz(DisasContext *s, arg_rprr_esz *a, uint32_t insn)
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#undef DO_ZPZZ
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/*
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*** SVE Integer Reduction Group
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*/
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typedef void gen_helper_gvec_reduc(TCGv_i64, TCGv_ptr, TCGv_ptr, TCGv_i32);
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static bool do_vpz_ool(DisasContext *s, arg_rpr_esz *a,
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gen_helper_gvec_reduc *fn)
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{
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unsigned vsz = vec_full_reg_size(s);
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TCGv_ptr t_zn, t_pg;
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TCGv_i32 desc;
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TCGv_i64 temp;
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if (fn == NULL) {
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return false;
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}
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if (!sve_access_check(s)) {
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return true;
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}
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desc = tcg_const_i32(simd_desc(vsz, vsz, 0));
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temp = tcg_temp_new_i64();
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t_zn = tcg_temp_new_ptr();
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t_pg = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn));
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tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg));
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fn(temp, t_zn, t_pg, desc);
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tcg_temp_free_ptr(t_zn);
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tcg_temp_free_ptr(t_pg);
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tcg_temp_free_i32(desc);
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write_fp_dreg(s, a->rd, temp);
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tcg_temp_free_i64(temp);
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return true;
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}
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#define DO_VPZ(NAME, name) \
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static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a, uint32_t insn) \
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{ \
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static gen_helper_gvec_reduc * const fns[4] = { \
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gen_helper_sve_##name##_b, gen_helper_sve_##name##_h, \
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gen_helper_sve_##name##_s, gen_helper_sve_##name##_d, \
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}; \
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return do_vpz_ool(s, a, fns[a->esz]); \
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}
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DO_VPZ(ORV, orv)
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DO_VPZ(ANDV, andv)
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DO_VPZ(EORV, eorv)
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DO_VPZ(UADDV, uaddv)
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DO_VPZ(SMAXV, smaxv)
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DO_VPZ(UMAXV, umaxv)
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DO_VPZ(SMINV, sminv)
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DO_VPZ(UMINV, uminv)
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static bool trans_SADDV(DisasContext *s, arg_rpr_esz *a, uint32_t insn)
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{
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static gen_helper_gvec_reduc * const fns[4] = {
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gen_helper_sve_saddv_b, gen_helper_sve_saddv_h,
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gen_helper_sve_saddv_s, NULL
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};
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return do_vpz_ool(s, a, fns[a->esz]);
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}
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#undef DO_VPZ
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/*
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*** SVE Predicate Logical Operations Group
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*/
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