mirror of https://gitee.com/openkylin/qemu.git
rtl8139: port to vmstate
Signed-off-by: Juan Quintela <quintela@redhat.com> Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Juan Quintela
Anthony Liguori
parent
9d29cdeaac
commit
060110c3e6
301
hw/rtl8139.c
301
hw/rtl8139.c
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@ -417,12 +417,6 @@ static void RTL8139TallyCounters_clear(RTL8139TallyCounters* counters);
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/* Writes tally counters to specified physical memory address */
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static void RTL8139TallyCounters_physical_memory_write(target_phys_addr_t tc_addr, RTL8139TallyCounters* counters);
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/* Loads values of tally counters from VM state file */
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static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters);
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/* Saves values of tally counters to VM state file */
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static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters);
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typedef struct RTL8139State {
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PCIDevice dev;
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uint8_t phys[8]; /* mac address */
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@ -1350,16 +1344,6 @@ static const VMStateDescription vmstate_tally_counters = {
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VMSTATE_END_OF_LIST()
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}
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};
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static void RTL8139TallyCounters_load(QEMUFile* f, RTL8139TallyCounters *tally_counters)
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{
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vmstate_load_state(f, &vmstate_tally_counters, tally_counters, vmstate_tally_counters.version_id);
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}
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/* Saves values of tally counters to VM state file */
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static void RTL8139TallyCounters_save(QEMUFile* f, RTL8139TallyCounters *tally_counters)
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{
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vmstate_save_state(f, &vmstate_tally_counters, tally_counters);
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}
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static void rtl8139_ChipCmd_write(RTL8139State *s, uint32_t val)
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{
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@ -3113,212 +3097,97 @@ static uint32_t rtl8139_mmio_readl(void *opaque, target_phys_addr_t addr)
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return val;
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}
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/* */
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static void rtl8139_save(QEMUFile* f,void* opaque)
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static int rtl8139_post_load(void *opaque, int version_id)
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{
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RTL8139State* s = opaque;
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unsigned int i;
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pci_device_save(&s->dev, f);
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qemu_put_buffer(f, s->phys, 6);
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qemu_put_buffer(f, s->mult, 8);
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for (i=0; i<4; ++i)
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{
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qemu_put_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
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}
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for (i=0; i<4; ++i)
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{
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qemu_put_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
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}
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qemu_put_be32s(f, &s->RxBuf); /* Receive buffer */
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qemu_put_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
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qemu_put_be32s(f, &s->RxBufPtr);
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qemu_put_be32s(f, &s->RxBufAddr);
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qemu_put_be16s(f, &s->IntrStatus);
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qemu_put_be16s(f, &s->IntrMask);
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qemu_put_be32s(f, &s->TxConfig);
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qemu_put_be32s(f, &s->RxConfig);
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qemu_put_be32s(f, &s->RxMissed);
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qemu_put_be16s(f, &s->CSCR);
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qemu_put_8s(f, &s->Cfg9346);
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qemu_put_8s(f, &s->Config0);
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qemu_put_8s(f, &s->Config1);
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qemu_put_8s(f, &s->Config3);
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qemu_put_8s(f, &s->Config4);
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qemu_put_8s(f, &s->Config5);
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qemu_put_8s(f, &s->clock_enabled);
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qemu_put_8s(f, &s->bChipCmdState);
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qemu_put_be16s(f, &s->MultiIntr);
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qemu_put_be16s(f, &s->BasicModeCtrl);
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qemu_put_be16s(f, &s->BasicModeStatus);
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qemu_put_be16s(f, &s->NWayAdvert);
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qemu_put_be16s(f, &s->NWayLPAR);
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qemu_put_be16s(f, &s->NWayExpansion);
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qemu_put_be16s(f, &s->CpCmd);
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qemu_put_8s(f, &s->TxThresh);
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i = 0;
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qemu_put_be32s(f, &i); /* unused. */
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qemu_put_buffer(f, s->conf.macaddr.a, 6);
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qemu_put_be32(f, s->rtl8139_mmio_io_addr);
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qemu_put_be32s(f, &s->currTxDesc);
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qemu_put_be32s(f, &s->currCPlusRxDesc);
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qemu_put_be32s(f, &s->currCPlusTxDesc);
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qemu_put_be32s(f, &s->RxRingAddrLO);
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qemu_put_be32s(f, &s->RxRingAddrHI);
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for (i=0; i<EEPROM_9346_SIZE; ++i)
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{
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qemu_put_be16s(f, &s->eeprom.contents[i]);
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}
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qemu_put_be32(f, s->eeprom.mode);
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qemu_put_be32s(f, &s->eeprom.tick);
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qemu_put_8s(f, &s->eeprom.address);
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qemu_put_be16s(f, &s->eeprom.input);
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qemu_put_be16s(f, &s->eeprom.output);
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qemu_put_8s(f, &s->eeprom.eecs);
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qemu_put_8s(f, &s->eeprom.eesk);
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qemu_put_8s(f, &s->eeprom.eedi);
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qemu_put_8s(f, &s->eeprom.eedo);
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qemu_put_be32s(f, &s->TCTR);
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qemu_put_be32s(f, &s->TimerInt);
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qemu_put_be64(f, s->TCTR_base);
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RTL8139TallyCounters_save(f, &s->tally_counters);
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qemu_put_be32s(f, &s->cplus_enabled);
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}
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static int rtl8139_load(QEMUFile* f,void* opaque,int version_id)
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{
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RTL8139State* s = opaque;
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unsigned int i;
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int ret;
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/* just 2 versions for now */
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if (version_id > 4)
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return -EINVAL;
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if (version_id >= 3) {
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ret = pci_device_load(&s->dev, f);
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if (ret < 0)
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return ret;
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}
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/* saved since version 1 */
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qemu_get_buffer(f, s->phys, 6);
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qemu_get_buffer(f, s->mult, 8);
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for (i=0; i<4; ++i)
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{
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qemu_get_be32s(f, &s->TxStatus[i]); /* TxStatus0 */
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}
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for (i=0; i<4; ++i)
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{
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qemu_get_be32s(f, &s->TxAddr[i]); /* TxAddr0 */
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}
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qemu_get_be32s(f, &s->RxBuf); /* Receive buffer */
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qemu_get_be32s(f, &s->RxBufferSize);/* internal variable, receive ring buffer size in C mode */
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qemu_get_be32s(f, &s->RxBufPtr);
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qemu_get_be32s(f, &s->RxBufAddr);
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qemu_get_be16s(f, &s->IntrStatus);
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qemu_get_be16s(f, &s->IntrMask);
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qemu_get_be32s(f, &s->TxConfig);
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qemu_get_be32s(f, &s->RxConfig);
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qemu_get_be32s(f, &s->RxMissed);
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qemu_get_be16s(f, &s->CSCR);
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qemu_get_8s(f, &s->Cfg9346);
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qemu_get_8s(f, &s->Config0);
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qemu_get_8s(f, &s->Config1);
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qemu_get_8s(f, &s->Config3);
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qemu_get_8s(f, &s->Config4);
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qemu_get_8s(f, &s->Config5);
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qemu_get_8s(f, &s->clock_enabled);
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qemu_get_8s(f, &s->bChipCmdState);
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qemu_get_be16s(f, &s->MultiIntr);
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qemu_get_be16s(f, &s->BasicModeCtrl);
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qemu_get_be16s(f, &s->BasicModeStatus);
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qemu_get_be16s(f, &s->NWayAdvert);
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qemu_get_be16s(f, &s->NWayLPAR);
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qemu_get_be16s(f, &s->NWayExpansion);
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qemu_get_be16s(f, &s->CpCmd);
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qemu_get_8s(f, &s->TxThresh);
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qemu_get_be32s(f, &i); /* unused. */
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qemu_get_buffer(f, s->conf.macaddr.a, 6);
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s->rtl8139_mmio_io_addr=qemu_get_be32(f);
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qemu_get_be32s(f, &s->currTxDesc);
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qemu_get_be32s(f, &s->currCPlusRxDesc);
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qemu_get_be32s(f, &s->currCPlusTxDesc);
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qemu_get_be32s(f, &s->RxRingAddrLO);
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qemu_get_be32s(f, &s->RxRingAddrHI);
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for (i=0; i<EEPROM_9346_SIZE; ++i)
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{
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qemu_get_be16s(f, &s->eeprom.contents[i]);
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}
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s->eeprom.mode=qemu_get_be32(f);
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qemu_get_be32s(f, &s->eeprom.tick);
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qemu_get_8s(f, &s->eeprom.address);
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qemu_get_be16s(f, &s->eeprom.input);
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qemu_get_be16s(f, &s->eeprom.output);
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qemu_get_8s(f, &s->eeprom.eecs);
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qemu_get_8s(f, &s->eeprom.eesk);
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qemu_get_8s(f, &s->eeprom.eedi);
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qemu_get_8s(f, &s->eeprom.eedo);
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/* saved since version 2 */
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if (version_id >= 2)
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{
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qemu_get_be32s(f, &s->TCTR);
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qemu_get_be32s(f, &s->TimerInt);
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s->TCTR_base=qemu_get_be64(f);
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RTL8139TallyCounters_load(f, &s->tally_counters);
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}
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else
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{
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/* not saved, use default */
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s->TCTR = 0;
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s->TimerInt = 0;
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s->TCTR_base = 0;
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RTL8139TallyCounters_clear(&s->tally_counters);
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}
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if (version_id >= 4) {
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qemu_get_be32s(f, &s->cplus_enabled);
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} else {
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if (version_id < 4) {
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s->cplus_enabled = s->CpCmd != 0;
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}
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return 0;
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}
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static const VMStateDescription vmstate_rtl8139 = {
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.name = "rtl8139",
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.version_id = 4,
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.minimum_version_id = 3,
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.minimum_version_id_old = 3,
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.post_load = rtl8139_post_load,
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.fields = (VMStateField []) {
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VMSTATE_PCI_DEVICE(dev, RTL8139State),
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VMSTATE_PARTIAL_BUFFER(phys, RTL8139State, 6),
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VMSTATE_BUFFER(mult, RTL8139State),
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VMSTATE_UINT32_ARRAY(TxStatus, RTL8139State, 4),
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VMSTATE_UINT32_ARRAY(TxAddr, RTL8139State, 4),
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VMSTATE_UINT32(RxBuf, RTL8139State),
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VMSTATE_UINT32(RxBufferSize, RTL8139State),
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VMSTATE_UINT32(RxBufPtr, RTL8139State),
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VMSTATE_UINT32(RxBufAddr, RTL8139State),
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VMSTATE_UINT16(IntrStatus, RTL8139State),
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VMSTATE_UINT16(IntrMask, RTL8139State),
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VMSTATE_UINT32(TxConfig, RTL8139State),
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VMSTATE_UINT32(RxConfig, RTL8139State),
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VMSTATE_UINT32(RxMissed, RTL8139State),
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VMSTATE_UINT16(CSCR, RTL8139State),
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VMSTATE_UINT8(Cfg9346, RTL8139State),
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VMSTATE_UINT8(Config0, RTL8139State),
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VMSTATE_UINT8(Config1, RTL8139State),
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VMSTATE_UINT8(Config3, RTL8139State),
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VMSTATE_UINT8(Config4, RTL8139State),
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VMSTATE_UINT8(Config5, RTL8139State),
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VMSTATE_UINT8(clock_enabled, RTL8139State),
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VMSTATE_UINT8(bChipCmdState, RTL8139State),
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VMSTATE_UINT16(MultiIntr, RTL8139State),
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VMSTATE_UINT16(BasicModeCtrl, RTL8139State),
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VMSTATE_UINT16(BasicModeStatus, RTL8139State),
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VMSTATE_UINT16(NWayAdvert, RTL8139State),
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VMSTATE_UINT16(NWayLPAR, RTL8139State),
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VMSTATE_UINT16(NWayExpansion, RTL8139State),
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VMSTATE_UINT16(CpCmd, RTL8139State),
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VMSTATE_UINT8(TxThresh, RTL8139State),
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VMSTATE_UNUSED(4),
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VMSTATE_MACADDR(conf.macaddr, RTL8139State),
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VMSTATE_INT32(rtl8139_mmio_io_addr, RTL8139State),
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VMSTATE_UINT32(currTxDesc, RTL8139State),
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VMSTATE_UINT32(currCPlusRxDesc, RTL8139State),
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VMSTATE_UINT32(currCPlusTxDesc, RTL8139State),
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VMSTATE_UINT32(RxRingAddrLO, RTL8139State),
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VMSTATE_UINT32(RxRingAddrHI, RTL8139State),
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VMSTATE_UINT16_ARRAY(eeprom.contents, RTL8139State, EEPROM_9346_SIZE),
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VMSTATE_INT32(eeprom.mode, RTL8139State),
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VMSTATE_UINT32(eeprom.tick, RTL8139State),
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VMSTATE_UINT8(eeprom.address, RTL8139State),
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VMSTATE_UINT16(eeprom.input, RTL8139State),
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VMSTATE_UINT16(eeprom.output, RTL8139State),
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VMSTATE_UINT8(eeprom.eecs, RTL8139State),
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VMSTATE_UINT8(eeprom.eesk, RTL8139State),
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VMSTATE_UINT8(eeprom.eedi, RTL8139State),
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VMSTATE_UINT8(eeprom.eedo, RTL8139State),
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VMSTATE_UINT32(TCTR, RTL8139State),
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VMSTATE_UINT32(TimerInt, RTL8139State),
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VMSTATE_INT64(TCTR_base, RTL8139State),
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VMSTATE_STRUCT(tally_counters, RTL8139State, 0,
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vmstate_tally_counters, RTL8139TallyCounters),
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VMSTATE_UINT32_V(cplus_enabled, RTL8139State, 4),
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VMSTATE_END_OF_LIST()
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}
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};
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/***********************************************************/
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/* PCI RTL8139 definitions */
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@ -3431,7 +3300,7 @@ static int pci_rtl8139_uninit(PCIDevice *dev)
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qemu_del_timer(s->timer);
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qemu_free_timer(s->timer);
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#endif
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unregister_savevm("rtl8139", s);
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vmstate_unregister(&vmstate_rtl8139, s);
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qemu_del_vlan_client(s->vc);
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return 0;
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}
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@ -3474,7 +3343,7 @@ static int pci_rtl8139_init(PCIDevice *dev)
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s->cplus_txbuffer_len = 0;
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s->cplus_txbuffer_offset = 0;
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register_savevm("rtl8139", -1, 4, rtl8139_save, rtl8139_load, s);
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vmstate_register(-1, &vmstate_rtl8139, s);
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#ifdef RTL8139_ONBOARD_TIMER
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s->timer = qemu_new_timer(vm_clock, rtl8139_timer, s);
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