mirror of https://gitee.com/openkylin/qemu.git
xlnx-zynqmp-rtc: Initial commit
Initial commit of the ZynqMP RTC device. Signed-off-by: Alistair Francis <alistair.francis@xilinx.com> Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Alistair Francis
Peter Maydell
parent
427cbc7e41
commit
07664ca68b
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@ -21,6 +21,7 @@ common-obj-$(CONFIG_IMX) += imx_epit.o
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common-obj-$(CONFIG_IMX) += imx_gpt.o
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common-obj-$(CONFIG_LM32) += lm32_timer.o
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common-obj-$(CONFIG_MILKYMIST) += milkymist-sysctl.o
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common-obj-$(CONFIG_XLNX_ZYNQMP) += xlnx-zynqmp-rtc.o
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obj-$(CONFIG_ALTERA_TIMER) += altera_timer.o
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obj-$(CONFIG_EXYNOS4) += exynos4210_mct.o
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@ -0,0 +1,214 @@
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/*
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* QEMU model of the Xilinx ZynqMP Real Time Clock (RTC).
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*
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* Copyright (c) 2017 Xilinx Inc.
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*
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* Written-by: Alistair Francis <alistair.francis@xilinx.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "qemu/osdep.h"
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#include "hw/sysbus.h"
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#include "hw/register.h"
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#include "qemu/bitops.h"
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#include "qemu/log.h"
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#include "hw/timer/xlnx-zynqmp-rtc.h"
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#ifndef XLNX_ZYNQMP_RTC_ERR_DEBUG
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#define XLNX_ZYNQMP_RTC_ERR_DEBUG 0
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#endif
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static void rtc_int_update_irq(XlnxZynqMPRTC *s)
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{
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bool pending = s->regs[R_RTC_INT_STATUS] & ~s->regs[R_RTC_INT_MASK];
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qemu_set_irq(s->irq_rtc_int, pending);
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}
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static void addr_error_int_update_irq(XlnxZynqMPRTC *s)
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{
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bool pending = s->regs[R_ADDR_ERROR] & ~s->regs[R_ADDR_ERROR_INT_MASK];
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qemu_set_irq(s->irq_addr_error_int, pending);
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}
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static void rtc_int_status_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
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rtc_int_update_irq(s);
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}
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static uint64_t rtc_int_en_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
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s->regs[R_RTC_INT_MASK] &= (uint32_t) ~val64;
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rtc_int_update_irq(s);
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return 0;
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}
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static uint64_t rtc_int_dis_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
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s->regs[R_RTC_INT_MASK] |= (uint32_t) val64;
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rtc_int_update_irq(s);
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return 0;
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}
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static void addr_error_postw(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
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addr_error_int_update_irq(s);
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}
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static uint64_t addr_error_int_en_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
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s->regs[R_ADDR_ERROR_INT_MASK] &= (uint32_t) ~val64;
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addr_error_int_update_irq(s);
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return 0;
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}
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static uint64_t addr_error_int_dis_prew(RegisterInfo *reg, uint64_t val64)
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{
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XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(reg->opaque);
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s->regs[R_ADDR_ERROR_INT_MASK] |= (uint32_t) val64;
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addr_error_int_update_irq(s);
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return 0;
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}
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static const RegisterAccessInfo rtc_regs_info[] = {
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{ .name = "SET_TIME_WRITE", .addr = A_SET_TIME_WRITE,
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},{ .name = "SET_TIME_READ", .addr = A_SET_TIME_READ,
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.ro = 0xffffffff,
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},{ .name = "CALIB_WRITE", .addr = A_CALIB_WRITE,
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},{ .name = "CALIB_READ", .addr = A_CALIB_READ,
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.ro = 0x1fffff,
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},{ .name = "CURRENT_TIME", .addr = A_CURRENT_TIME,
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.ro = 0xffffffff,
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},{ .name = "CURRENT_TICK", .addr = A_CURRENT_TICK,
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.ro = 0xffff,
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},{ .name = "ALARM", .addr = A_ALARM,
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},{ .name = "RTC_INT_STATUS", .addr = A_RTC_INT_STATUS,
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.w1c = 0x3,
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.post_write = rtc_int_status_postw,
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},{ .name = "RTC_INT_MASK", .addr = A_RTC_INT_MASK,
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.reset = 0x3,
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.ro = 0x3,
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},{ .name = "RTC_INT_EN", .addr = A_RTC_INT_EN,
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.pre_write = rtc_int_en_prew,
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},{ .name = "RTC_INT_DIS", .addr = A_RTC_INT_DIS,
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.pre_write = rtc_int_dis_prew,
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},{ .name = "ADDR_ERROR", .addr = A_ADDR_ERROR,
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.w1c = 0x1,
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.post_write = addr_error_postw,
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},{ .name = "ADDR_ERROR_INT_MASK", .addr = A_ADDR_ERROR_INT_MASK,
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.reset = 0x1,
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.ro = 0x1,
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},{ .name = "ADDR_ERROR_INT_EN", .addr = A_ADDR_ERROR_INT_EN,
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.pre_write = addr_error_int_en_prew,
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},{ .name = "ADDR_ERROR_INT_DIS", .addr = A_ADDR_ERROR_INT_DIS,
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.pre_write = addr_error_int_dis_prew,
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},{ .name = "CONTROL", .addr = A_CONTROL,
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.reset = 0x1000000,
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.rsvd = 0x70fffffe,
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},{ .name = "SAFETY_CHK", .addr = A_SAFETY_CHK,
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}
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};
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static void rtc_reset(DeviceState *dev)
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{
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XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(dev);
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unsigned int i;
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for (i = 0; i < ARRAY_SIZE(s->regs_info); ++i) {
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register_reset(&s->regs_info[i]);
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}
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rtc_int_update_irq(s);
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addr_error_int_update_irq(s);
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}
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static const MemoryRegionOps rtc_ops = {
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.read = register_read_memory,
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.write = register_write_memory,
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.endianness = DEVICE_LITTLE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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};
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static void rtc_init(Object *obj)
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{
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XlnxZynqMPRTC *s = XLNX_ZYNQMP_RTC(obj);
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SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
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RegisterInfoArray *reg_array;
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memory_region_init(&s->iomem, obj, TYPE_XLNX_ZYNQMP_RTC,
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XLNX_ZYNQMP_RTC_R_MAX * 4);
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reg_array =
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register_init_block32(DEVICE(obj), rtc_regs_info,
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ARRAY_SIZE(rtc_regs_info),
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s->regs_info, s->regs,
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&rtc_ops,
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XLNX_ZYNQMP_RTC_ERR_DEBUG,
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XLNX_ZYNQMP_RTC_R_MAX * 4);
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memory_region_add_subregion(&s->iomem,
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0x0,
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®_array->mem);
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sysbus_init_mmio(sbd, &s->iomem);
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sysbus_init_irq(sbd, &s->irq_rtc_int);
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sysbus_init_irq(sbd, &s->irq_addr_error_int);
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}
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static const VMStateDescription vmstate_rtc = {
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.name = TYPE_XLNX_ZYNQMP_RTC,
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.version_id = 1,
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.minimum_version_id = 1,
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.fields = (VMStateField[]) {
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VMSTATE_UINT32_ARRAY(regs, XlnxZynqMPRTC, XLNX_ZYNQMP_RTC_R_MAX),
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VMSTATE_END_OF_LIST(),
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}
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};
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static void rtc_class_init(ObjectClass *klass, void *data)
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{
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DeviceClass *dc = DEVICE_CLASS(klass);
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dc->reset = rtc_reset;
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dc->vmsd = &vmstate_rtc;
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}
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static const TypeInfo rtc_info = {
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.name = TYPE_XLNX_ZYNQMP_RTC,
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(XlnxZynqMPRTC),
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.class_init = rtc_class_init,
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.instance_init = rtc_init,
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};
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static void rtc_register_types(void)
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{
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type_register_static(&rtc_info);
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}
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type_init(rtc_register_types)
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@ -0,0 +1,84 @@
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/*
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* QEMU model of the Xilinx ZynqMP Real Time Clock (RTC).
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*
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* Copyright (c) 2017 Xilinx Inc.
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*
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* Written-by: Alistair Francis <alistair.francis@xilinx.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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#include "hw/register.h"
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#define TYPE_XLNX_ZYNQMP_RTC "xlnx-zynmp.rtc"
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#define XLNX_ZYNQMP_RTC(obj) \
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OBJECT_CHECK(XlnxZynqMPRTC, (obj), TYPE_XLNX_ZYNQMP_RTC)
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REG32(SET_TIME_WRITE, 0x0)
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REG32(SET_TIME_READ, 0x4)
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REG32(CALIB_WRITE, 0x8)
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FIELD(CALIB_WRITE, FRACTION_EN, 20, 1)
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FIELD(CALIB_WRITE, FRACTION_DATA, 16, 4)
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FIELD(CALIB_WRITE, MAX_TICK, 0, 16)
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REG32(CALIB_READ, 0xc)
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FIELD(CALIB_READ, FRACTION_EN, 20, 1)
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FIELD(CALIB_READ, FRACTION_DATA, 16, 4)
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FIELD(CALIB_READ, MAX_TICK, 0, 16)
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REG32(CURRENT_TIME, 0x10)
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REG32(CURRENT_TICK, 0x14)
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FIELD(CURRENT_TICK, VALUE, 0, 16)
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REG32(ALARM, 0x18)
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REG32(RTC_INT_STATUS, 0x20)
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FIELD(RTC_INT_STATUS, ALARM, 1, 1)
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FIELD(RTC_INT_STATUS, SECONDS, 0, 1)
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REG32(RTC_INT_MASK, 0x24)
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FIELD(RTC_INT_MASK, ALARM, 1, 1)
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FIELD(RTC_INT_MASK, SECONDS, 0, 1)
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REG32(RTC_INT_EN, 0x28)
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FIELD(RTC_INT_EN, ALARM, 1, 1)
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FIELD(RTC_INT_EN, SECONDS, 0, 1)
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REG32(RTC_INT_DIS, 0x2c)
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FIELD(RTC_INT_DIS, ALARM, 1, 1)
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FIELD(RTC_INT_DIS, SECONDS, 0, 1)
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REG32(ADDR_ERROR, 0x30)
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FIELD(ADDR_ERROR, STATUS, 0, 1)
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REG32(ADDR_ERROR_INT_MASK, 0x34)
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FIELD(ADDR_ERROR_INT_MASK, MASK, 0, 1)
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REG32(ADDR_ERROR_INT_EN, 0x38)
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FIELD(ADDR_ERROR_INT_EN, MASK, 0, 1)
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REG32(ADDR_ERROR_INT_DIS, 0x3c)
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FIELD(ADDR_ERROR_INT_DIS, MASK, 0, 1)
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REG32(CONTROL, 0x40)
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FIELD(CONTROL, BATTERY_DISABLE, 31, 1)
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FIELD(CONTROL, OSC_CNTRL, 24, 4)
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FIELD(CONTROL, SLVERR_ENABLE, 0, 1)
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REG32(SAFETY_CHK, 0x50)
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#define XLNX_ZYNQMP_RTC_R_MAX (R_SAFETY_CHK + 1)
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typedef struct XlnxZynqMPRTC {
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SysBusDevice parent_obj;
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MemoryRegion iomem;
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qemu_irq irq_rtc_int;
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qemu_irq irq_addr_error_int;
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uint32_t regs[XLNX_ZYNQMP_RTC_R_MAX];
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RegisterInfo regs_info[XLNX_ZYNQMP_RTC_R_MAX];
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} XlnxZynqMPRTC;
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