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Less hardcoding of TARGET_USER_ONLY. 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4928 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2008-07-23 16:14:22 +00:00
parent 477e3edf8b
commit 0eaef5aa01
6 changed files with 290 additions and 393 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

9
target-mips/cpu.h
View File

@ -445,17 +445,12 @@ struct CPUMIPSState {
uint32_t CP0_TCStatus_rw_bitmask; /* Read/write bits in CP0_TCStatus */
int insn_flags; /* Supported instruction set */
#ifdef CONFIG_USER_ONLY
target_ulong tls_value;
#endif
target_ulong tls_value; /* For usermode emulation */
CPU_COMMON
const mips_def_t *cpu_model;
#ifndef CONFIG_USER_ONLY
void *irq[8];
#endif
struct QEMUTimer *timer; /* Internal timer */
};
@ -494,7 +489,6 @@ static inline int cpu_mmu_index (CPUState *env)
return env->hflags & MIPS_HFLAG_KSU;
}
#if defined(CONFIG_USER_ONLY)
static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
{
if (newsp)
@ -502,7 +496,6 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
env->active_tc.gpr[7] = 0;
env->active_tc.gpr[2] = 0;
}
#endif
#include "cpu-all.h"

440
target-mips/helper.c
View File

@ -206,26 +206,23 @@ static int get_physical_address (CPUState *env, target_ulong *physical,
return ret;
}
#if defined(CONFIG_USER_ONLY)
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
return addr;
}
#else
target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
{
target_ulong phys_addr;
int prot;
if (env->user_mode_only)
return addr;
else {
target_ulong phys_addr;
int prot;
if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
return -1;
return phys_addr;
if (get_physical_address(env, &phys_addr, &prot, addr, 0, ACCESS_INT) != 0)
return -1;
return phys_addr;
}
}
void cpu_mips_init_mmu (CPUState *env)
{
}
#endif /* !defined(CONFIG_USER_ONLY) */
int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
int mmu_idx, int is_softmmu)
@ -318,7 +315,6 @@ int cpu_mips_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
return ret;
}
#if !defined(CONFIG_USER_ONLY)
static const char * const excp_names[EXCP_LAST + 1] = {
[EXCP_RESET] = "reset",
[EXCP_SRESET] = "soft reset",
@ -354,232 +350,230 @@ static const char * const excp_names[EXCP_LAST + 1] = {
[EXCP_C2E] = "precise coprocessor 2",
[EXCP_CACHE] = "cache error",
};
#endif
void do_interrupt (CPUState *env)
{
#if !defined(CONFIG_USER_ONLY)
target_ulong offset;
int cause = -1;
const char *name;
if (!env->user_mode_only) {
target_ulong offset;
int cause = -1;
const char *name;
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
name = "unknown";
else
name = excp_names[env->exception_index];
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
if (env->exception_index < 0 || env->exception_index > EXCP_LAST)
name = "unknown";
else
name = excp_names[env->exception_index];
fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
__func__, env->active_tc.PC, env->CP0_EPC, name);
}
if (env->exception_index == EXCP_EXT_INTERRUPT &&
(env->hflags & MIPS_HFLAG_DM))
env->exception_index = EXCP_DINT;
offset = 0x180;
switch (env->exception_index) {
case EXCP_DSS:
env->CP0_Debug |= 1 << CP0DB_DSS;
/* Debug single step cannot be raised inside a delay slot and
* resume will always occur on the next instruction
* (but we assume the pc has always been updated during
* code translation).
*/
env->CP0_DEPC = env->active_tc.PC;
goto enter_debug_mode;
case EXCP_DINT:
env->CP0_Debug |= 1 << CP0DB_DINT;
goto set_DEPC;
case EXCP_DIB:
env->CP0_Debug |= 1 << CP0DB_DIB;
goto set_DEPC;
case EXCP_DBp:
env->CP0_Debug |= 1 << CP0DB_DBp;
goto set_DEPC;
case EXCP_DDBS:
env->CP0_Debug |= 1 << CP0DB_DDBS;
goto set_DEPC;
case EXCP_DDBL:
env->CP0_Debug |= 1 << CP0DB_DDBL;
set_DEPC:
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
come back to the jump. */
env->CP0_DEPC = env->active_tc.PC - 4;
env->hflags &= ~MIPS_HFLAG_BMASK;
} else {
fprintf(logfile, "%s enter: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " %s exception\n",
__func__, env->active_tc.PC, env->CP0_EPC, name);
}
if (env->exception_index == EXCP_EXT_INTERRUPT &&
(env->hflags & MIPS_HFLAG_DM))
env->exception_index = EXCP_DINT;
offset = 0x180;
switch (env->exception_index) {
case EXCP_DSS:
env->CP0_Debug |= 1 << CP0DB_DSS;
/* Debug single step cannot be raised inside a delay slot and
resume will always occur on the next instruction
(but we assume the pc has always been updated during
code translation). */
env->CP0_DEPC = env->active_tc.PC;
}
enter_debug_mode:
env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
env->hflags &= ~(MIPS_HFLAG_KSU);
/* EJTAG probe trap enable is not implemented... */
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD);
env->active_tc.PC = (int32_t)0xBFC00480;
break;
case EXCP_RESET:
cpu_reset(env);
break;
case EXCP_SRESET:
env->CP0_Status |= (1 << CP0St_SR);
memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
goto set_error_EPC;
case EXCP_NMI:
env->CP0_Status |= (1 << CP0St_NMI);
set_error_EPC:
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
come back to the jump. */
env->CP0_ErrorEPC = env->active_tc.PC - 4;
env->hflags &= ~MIPS_HFLAG_BMASK;
} else {
env->CP0_ErrorEPC = env->active_tc.PC;
}
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
env->hflags &= ~(MIPS_HFLAG_KSU);
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD);
env->active_tc.PC = (int32_t)0xBFC00000;
break;
case EXCP_EXT_INTERRUPT:
cause = 0;
if (env->CP0_Cause & (1 << CP0Ca_IV))
offset = 0x200;
goto set_EPC;
case EXCP_LTLBL:
cause = 1;
goto set_EPC;
case EXCP_TLBL:
cause = 2;
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
#if defined(TARGET_MIPS64)
int R = env->CP0_BadVAddr >> 62;
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
offset = 0x080;
else
#endif
offset = 0x000;
}
goto set_EPC;
case EXCP_TLBS:
cause = 3;
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
#if defined(TARGET_MIPS64)
int R = env->CP0_BadVAddr >> 62;
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
offset = 0x080;
else
#endif
offset = 0x000;
}
goto set_EPC;
case EXCP_AdEL:
cause = 4;
goto set_EPC;
case EXCP_AdES:
cause = 5;
goto set_EPC;
case EXCP_IBE:
cause = 6;
goto set_EPC;
case EXCP_DBE:
cause = 7;
goto set_EPC;
case EXCP_SYSCALL:
cause = 8;
goto set_EPC;
case EXCP_BREAK:
cause = 9;
goto set_EPC;
case EXCP_RI:
cause = 10;
goto set_EPC;
case EXCP_CpU:
cause = 11;
env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
(env->error_code << CP0Ca_CE);
goto set_EPC;
case EXCP_OVERFLOW:
cause = 12;
goto set_EPC;
case EXCP_TRAP:
cause = 13;
goto set_EPC;
case EXCP_FPE:
cause = 15;
goto set_EPC;
case EXCP_C2E:
cause = 18;
goto set_EPC;
case EXCP_MDMX:
cause = 22;
goto set_EPC;
case EXCP_DWATCH:
cause = 23;
/* XXX: TODO: manage defered watch exceptions */
goto set_EPC;
case EXCP_MCHECK:
cause = 24;
goto set_EPC;
case EXCP_THREAD:
cause = 25;
goto set_EPC;
case EXCP_CACHE:
cause = 30;
if (env->CP0_Status & (1 << CP0St_BEV)) {
offset = 0x100;
} else {
offset = 0x20000100;
}
set_EPC:
if (!(env->CP0_Status & (1 << CP0St_EXL))) {
goto enter_debug_mode;
case EXCP_DINT:
env->CP0_Debug |= 1 << CP0DB_DINT;
goto set_DEPC;
case EXCP_DIB:
env->CP0_Debug |= 1 << CP0DB_DIB;
goto set_DEPC;
case EXCP_DBp:
env->CP0_Debug |= 1 << CP0DB_DBp;
goto set_DEPC;
case EXCP_DDBS:
env->CP0_Debug |= 1 << CP0DB_DDBS;
goto set_DEPC;
case EXCP_DDBL:
env->CP0_Debug |= 1 << CP0DB_DDBL;
set_DEPC:
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
come back to the jump. */
env->CP0_EPC = env->active_tc.PC - 4;
env->CP0_Cause |= (1 << CP0Ca_BD);
env->CP0_DEPC = env->active_tc.PC - 4;
env->hflags &= ~MIPS_HFLAG_BMASK;
} else {
env->CP0_EPC = env->active_tc.PC;
env->CP0_Cause &= ~(1 << CP0Ca_BD);
env->CP0_DEPC = env->active_tc.PC;
}
env->CP0_Status |= (1 << CP0St_EXL);
enter_debug_mode:
env->hflags |= MIPS_HFLAG_DM | MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
env->hflags &= ~(MIPS_HFLAG_KSU);
/* EJTAG probe trap enable is not implemented... */
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD);
env->active_tc.PC = (int32_t)0xBFC00480;
break;
case EXCP_RESET:
cpu_reset(env);
break;
case EXCP_SRESET:
env->CP0_Status |= (1 << CP0St_SR);
memset(env->CP0_WatchLo, 0, sizeof(*env->CP0_WatchLo));
goto set_error_EPC;
case EXCP_NMI:
env->CP0_Status |= (1 << CP0St_NMI);
set_error_EPC:
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
come back to the jump. */
env->CP0_ErrorEPC = env->active_tc.PC - 4;
env->hflags &= ~MIPS_HFLAG_BMASK;
} else {
env->CP0_ErrorEPC = env->active_tc.PC;
}
env->CP0_Status |= (1 << CP0St_ERL) | (1 << CP0St_BEV);
env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
env->hflags &= ~(MIPS_HFLAG_KSU);
if (!(env->CP0_Status & (1 << CP0St_EXL)))
env->CP0_Cause &= ~(1 << CP0Ca_BD);
env->active_tc.PC = (int32_t)0xBFC00000;
break;
case EXCP_EXT_INTERRUPT:
cause = 0;
if (env->CP0_Cause & (1 << CP0Ca_IV))
offset = 0x200;
goto set_EPC;
case EXCP_LTLBL:
cause = 1;
goto set_EPC;
case EXCP_TLBL:
cause = 2;
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
#if defined(TARGET_MIPS64)
int R = env->CP0_BadVAddr >> 62;
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
offset = 0x080;
else
#endif
offset = 0x000;
}
goto set_EPC;
case EXCP_TLBS:
cause = 3;
if (env->error_code == 1 && !(env->CP0_Status & (1 << CP0St_EXL))) {
#if defined(TARGET_MIPS64)
int R = env->CP0_BadVAddr >> 62;
int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0;
int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0;
int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0;
if ((R == 0 && UX) || (R == 1 && SX) || (R == 3 && KX))
offset = 0x080;
else
#endif
offset = 0x000;
}
goto set_EPC;
case EXCP_AdEL:
cause = 4;
goto set_EPC;
case EXCP_AdES:
cause = 5;
goto set_EPC;
case EXCP_IBE:
cause = 6;
goto set_EPC;
case EXCP_DBE:
cause = 7;
goto set_EPC;
case EXCP_SYSCALL:
cause = 8;
goto set_EPC;
case EXCP_BREAK:
cause = 9;
goto set_EPC;
case EXCP_RI:
cause = 10;
goto set_EPC;
case EXCP_CpU:
cause = 11;
env->CP0_Cause = (env->CP0_Cause & ~(0x3 << CP0Ca_CE)) |
(env->error_code << CP0Ca_CE);
goto set_EPC;
case EXCP_OVERFLOW:
cause = 12;
goto set_EPC;
case EXCP_TRAP:
cause = 13;
goto set_EPC;
case EXCP_FPE:
cause = 15;
goto set_EPC;
case EXCP_C2E:
cause = 18;
goto set_EPC;
case EXCP_MDMX:
cause = 22;
goto set_EPC;
case EXCP_DWATCH:
cause = 23;
/* XXX: TODO: manage defered watch exceptions */
goto set_EPC;
case EXCP_MCHECK:
cause = 24;
goto set_EPC;
case EXCP_THREAD:
cause = 25;
goto set_EPC;
case EXCP_CACHE:
cause = 30;
if (env->CP0_Status & (1 << CP0St_BEV)) {
offset = 0x100;
} else {
offset = 0x20000100;
}
set_EPC:
if (!(env->CP0_Status & (1 << CP0St_EXL))) {
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
come back to the jump. */
env->CP0_EPC = env->active_tc.PC - 4;
env->CP0_Cause |= (1 << CP0Ca_BD);
} else {
env->CP0_EPC = env->active_tc.PC;
env->CP0_Cause &= ~(1 << CP0Ca_BD);
}
env->CP0_Status |= (1 << CP0St_EXL);
env->hflags |= MIPS_HFLAG_64 | MIPS_HFLAG_CP0;
env->hflags &= ~(MIPS_HFLAG_KSU);
}
env->hflags &= ~MIPS_HFLAG_BMASK;
if (env->CP0_Status & (1 << CP0St_BEV)) {
env->active_tc.PC = (int32_t)0xBFC00200;
} else {
env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
}
env->active_tc.PC += offset;
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
break;
default:
if (logfile) {
fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
env->exception_index);
}
printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
exit(1);
}
env->hflags &= ~MIPS_HFLAG_BMASK;
if (env->CP0_Status & (1 << CP0St_BEV)) {
env->active_tc.PC = (int32_t)0xBFC00200;
} else {
env->active_tc.PC = (int32_t)(env->CP0_EBase & ~0x3ff);
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
__func__, env->active_tc.PC, env->CP0_EPC, cause,
env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
env->CP0_DEPC);
}
env->active_tc.PC += offset;
env->CP0_Cause = (env->CP0_Cause & ~(0x1f << CP0Ca_EC)) | (cause << CP0Ca_EC);
break;
default:
if (logfile) {
fprintf(logfile, "Invalid MIPS exception %d. Exiting\n",
env->exception_index);
}
printf("Invalid MIPS exception %d. Exiting\n", env->exception_index);
exit(1);
}
if (logfile && env->exception_index != EXCP_EXT_INTERRUPT) {
fprintf(logfile, "%s: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx " cause %d\n"
" S %08x C %08x A " TARGET_FMT_lx " D " TARGET_FMT_lx "\n",
__func__, env->active_tc.PC, env->CP0_EPC, cause,
env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr,
env->CP0_DEPC);
}
#endif /* !defined(CONFIG_USER_ONLY) */
env->exception_index = EXCP_NONE;
}

6
target-mips/helper.h
View File

@ -41,8 +41,8 @@ DEF_HELPER(target_ulong, do_macchiu, (target_ulong t0, target_ulong t1))
DEF_HELPER(target_ulong, do_msachi, (target_ulong t0, target_ulong t1))
DEF_HELPER(target_ulong, do_msachiu, (target_ulong t0, target_ulong t1))
/* CP0 helpers */
#ifndef CONFIG_USER_ONLY
/* CP0 helpers */
DEF_HELPER(target_ulong, do_mfc0_mvpcontrol, (void))
DEF_HELPER(target_ulong, do_mfc0_mvpconf0, (void))
DEF_HELPER(target_ulong, do_mfc0_mvpconf1, (void))
@ -135,7 +135,6 @@ DEF_HELPER(void, do_mtc0_taglo, (target_ulong t0))
DEF_HELPER(void, do_mtc0_datalo, (target_ulong t0))
DEF_HELPER(void, do_mtc0_taghi, (target_ulong t0))
DEF_HELPER(void, do_mtc0_datahi, (target_ulong t0))
#endif /* !CONFIG_USER_ONLY */
/* MIPS MT functions */
DEF_HELPER(target_ulong, do_mftgpr, (target_ulong t0, uint32_t sel))
@ -152,6 +151,7 @@ DEF_HELPER(target_ulong, do_dmt, (target_ulong t0))
DEF_HELPER(target_ulong, do_emt, (target_ulong t0))
DEF_HELPER(target_ulong, do_dvpe, (target_ulong t0))
DEF_HELPER(target_ulong, do_evpe, (target_ulong t0))
#endif /* !CONFIG_USER_ONLY */
DEF_HELPER(void, do_fork, (target_ulong t0, target_ulong t1))
DEF_HELPER(target_ulong, do_yield, (target_ulong t0))
@ -257,10 +257,12 @@ FOP_PROTO(ngt)
#undef FOP_PROTO
/* Special functions */
#ifndef CONFIG_USER_ONLY
DEF_HELPER(target_ulong, do_di, (void))
DEF_HELPER(target_ulong, do_ei, (void))
DEF_HELPER(void, do_eret, (void))
DEF_HELPER(void, do_deret, (void))
#endif /* !CONFIG_USER_ONLY */
DEF_HELPER(target_ulong, do_rdhwr_cpunum, (void))
DEF_HELPER(target_ulong, do_rdhwr_synci_step, (void))
DEF_HELPER(target_ulong, do_rdhwr_cc, (void))

95
target-mips/op_helper.c
View File

@ -596,59 +596,7 @@ void do_sdr(target_ulong t0, target_ulong t1, int mem_idx)
}
#endif /* TARGET_MIPS64 */
#ifdef CONFIG_USER_ONLY
void do_mfc0_random (void)
{
cpu_abort(env, "mfc0 random\n");
}
void do_mfc0_count (void)
{
cpu_abort(env, "mfc0 count\n");
}
void cpu_mips_store_count(CPUState *env, uint32_t value)
{
cpu_abort(env, "mtc0 count\n");
}
void cpu_mips_store_compare(CPUState *env, uint32_t value)
{
cpu_abort(env, "mtc0 compare\n");
}
void cpu_mips_start_count(CPUState *env)
{
cpu_abort(env, "start count\n");
}
void cpu_mips_stop_count(CPUState *env)
{
cpu_abort(env, "stop count\n");
}
void cpu_mips_update_irq(CPUState *env)
{
cpu_abort(env, "mtc0 status / mtc0 cause\n");
}
void do_mtc0_status_debug(uint32_t old, uint32_t val)
{
cpu_abort(env, "mtc0 status debug\n");
}
void do_mtc0_status_irqraise_debug (void)
{
cpu_abort(env, "mtc0 status irqraise debug\n");
}
void cpu_mips_tlb_flush (CPUState *env, int flush_global)
{
cpu_abort(env, "mips_tlb_flush\n");
}
#else
#ifndef CONFIG_USER_ONLY
/* CP0 helpers */
target_ulong do_mfc0_mvpcontrol (void)
{
@ -1582,44 +1530,6 @@ target_ulong do_yield(target_ulong t0)
return env->CP0_YQMask;
}
/* CP1 functions */
void fpu_handle_exception(void)
{
#ifdef CONFIG_SOFTFLOAT
int flags = get_float_exception_flags(&env->fpu->fp_status);
unsigned int cpuflags = 0, enable, cause = 0;
enable = GET_FP_ENABLE(env->fpu->fcr31);
/* determine current flags */
if (flags & float_flag_invalid) {
cpuflags |= FP_INVALID;
cause |= FP_INVALID & enable;
}
if (flags & float_flag_divbyzero) {
cpuflags |= FP_DIV0;
cause |= FP_DIV0 & enable;
}
if (flags & float_flag_overflow) {
cpuflags |= FP_OVERFLOW;
cause |= FP_OVERFLOW & enable;
}
if (flags & float_flag_underflow) {
cpuflags |= FP_UNDERFLOW;
cause |= FP_UNDERFLOW & enable;
}
if (flags & float_flag_inexact) {
cpuflags |= FP_INEXACT;
cause |= FP_INEXACT & enable;
}
SET_FP_FLAGS(env->fpu->fcr31, cpuflags);
SET_FP_CAUSE(env->fpu->fcr31, cause);
#else
SET_FP_FLAGS(env->fpu->fcr31, 0);
SET_FP_CAUSE(env->fpu->fcr31, 0);
#endif
}
#ifndef CONFIG_USER_ONLY
/* TLB management */
void cpu_mips_tlb_flush (CPUState *env, int flush_global)
@ -1743,8 +1653,6 @@ void r4k_do_tlbr (void)
(tlb->C1 << 3) | (tlb->PFN[1] >> 6);
}
#endif /* !CONFIG_USER_ONLY */
/* Specials */
target_ulong do_di (void)
{
@ -1821,6 +1729,7 @@ void do_deret (void)
debug_post_eret();
env->CP0_LLAddr = 1;
}
#endif /* !CONFIG_USER_ONLY */
target_ulong do_rdhwr_cpunum(void)
{

106
target-mips/translate.c
View File

@ -2808,8 +2808,8 @@ fail:
tcg_temp_free(t1);
}
/* CP0 (MMU and control) */
#ifndef CONFIG_USER_ONLY
/* CP0 (MMU and control) */
static inline void gen_mfc0_load32 (TCGv t, target_ulong off)
{
TCGv r_tmp = tcg_temp_new(TCG_TYPE_I32);
@ -8052,12 +8052,13 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
tcg_gen_helper_1_0(do_rdhwr_ccres, t0);
break;
case 29:
#if defined (CONFIG_USER_ONLY)
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value));
break;
#else
/* XXX: Some CPUs implement this in hardware. Not supported yet. */
#endif
if (env->user_mode_only) {
tcg_gen_ld_tl(t0, cpu_env, offsetof(CPUState, tls_value));
break;
} else {
/* XXX: Some CPUs implement this in hardware.
Not supported yet. */
}
default: /* Invalid */
MIPS_INVAL("rdhwr");
generate_exception(ctx, EXCP_RI);
@ -8166,20 +8167,22 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
case OPC_DMTC0:
#endif
#ifndef CONFIG_USER_ONLY
gen_cp0(env, ctx, op1, rt, rd);
#endif
if (!env->user_mode_only)
gen_cp0(env, ctx, op1, rt, rd);
#endif /* !CONFIG_USER_ONLY */
break;
case OPC_C0_FIRST ... OPC_C0_LAST:
#ifndef CONFIG_USER_ONLY
gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
#endif
if (!env->user_mode_only)
gen_cp0(env, ctx, MASK_C0(ctx->opcode), rt, rd);
#endif /* !CONFIG_USER_ONLY */
break;
case OPC_MFMC0:
#ifndef CONFIG_USER_ONLY
op2 = MASK_MFMC0(ctx->opcode);
{
if (!env->user_mode_only) {
TCGv t0 = tcg_temp_local_new(TCG_TYPE_TL);
op2 = MASK_MFMC0(ctx->opcode);
switch (op2) {
case OPC_DMT:
check_insn(env, ctx, ASE_MT);
@ -8219,7 +8222,7 @@ static void decode_opc (CPUState *env, DisasContext *ctx)
gen_store_gpr(t0, rt);
tcg_temp_free(t0);
}
#endif
#endif /* !CONFIG_USER_ONLY */
break;
case OPC_RDPGPR:
check_insn(env, ctx, ISA_MIPS32R2);
@ -8474,11 +8477,10 @@ gen_intermediate_code_internal (CPUState *env, TranslationBlock *tb,
/* Restore delay slot state from the tb context. */
ctx.hflags = (uint32_t)tb->flags; /* FIXME: maybe use 64 bits here? */
restore_cpu_state(env, &ctx);
#if defined(CONFIG_USER_ONLY)
ctx.mem_idx = MIPS_HFLAG_UM;
#else
ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
#endif
if (env->user_mode_only)
ctx.mem_idx = MIPS_HFLAG_UM;
else
ctx.mem_idx = ctx.hflags & MIPS_HFLAG_KSU;
num_insns = 0;
max_insns = tb->cflags & CF_COUNT_MASK;
if (max_insns == 0)
@ -8759,42 +8761,42 @@ void cpu_reset (CPUMIPSState *env)
tlb_flush(env, 1);
/* Minimal init */
#if !defined(CONFIG_USER_ONLY)
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
* come back to the jump. */
env->CP0_ErrorEPC = env->active_tc.PC - 4;
} else {
env->CP0_ErrorEPC = env->active_tc.PC;
}
env->active_tc.PC = (int32_t)0xBFC00000;
env->CP0_Wired = 0;
/* SMP not implemented */
env->CP0_EBase = 0x80000000;
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
/* vectored interrupts not implemented, timer on int 7,
no performance counters. */
env->CP0_IntCtl = 0xe0000000;
{
int i;
for (i = 0; i < 7; i++) {
env->CP0_WatchLo[i] = 0;
env->CP0_WatchHi[i] = 0x80000000;
}
env->CP0_WatchLo[7] = 0;
env->CP0_WatchHi[7] = 0;
}
/* Count register increments in debug mode, EJTAG version 1 */
env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
#endif
env->exception_index = EXCP_NONE;
#if defined(CONFIG_USER_ONLY)
env->hflags = MIPS_HFLAG_UM;
env->user_mode_only = 1;
#else
env->hflags = MIPS_HFLAG_CP0;
#endif
if (env->user_mode_only) {
env->hflags = MIPS_HFLAG_UM;
} else {
if (env->hflags & MIPS_HFLAG_BMASK) {
/* If the exception was raised from a delay slot,
come back to the jump. */
env->CP0_ErrorEPC = env->active_tc.PC - 4;
} else {
env->CP0_ErrorEPC = env->active_tc.PC;
}
env->active_tc.PC = (int32_t)0xBFC00000;
env->CP0_Wired = 0;
/* SMP not implemented */
env->CP0_EBase = 0x80000000;
env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL);
/* vectored interrupts not implemented, timer on int 7,
no performance counters. */
env->CP0_IntCtl = 0xe0000000;
{
int i;
for (i = 0; i < 7; i++) {
env->CP0_WatchLo[i] = 0;
env->CP0_WatchHi[i] = 0x80000000;
}
env->CP0_WatchLo[7] = 0;
env->CP0_WatchHi[7] = 0;
}
/* Count register increments in debug mode, EJTAG version 1 */
env->CP0_Debug = (1 << CP0DB_CNT) | (0x1 << CP0DB_VER);
env->hflags = MIPS_HFLAG_CP0;
}
env->exception_index = EXCP_NONE;
cpu_mips_register(env, env->cpu_model);
}

27
target-mips/translate_init.c
View File

@ -439,7 +439,6 @@ void mips_cpu_list (FILE *f, int (*cpu_fprintf)(FILE *f, const char *fmt, ...))
}
}
#ifndef CONFIG_USER_ONLY
static void no_mmu_init (CPUMIPSState *env, const mips_def_t *def)
{
env->tlb->nb_tlb = 1;
@ -485,21 +484,20 @@ static void mmu_init (CPUMIPSState *env, const mips_def_t *def)
env->CP0_Random = env->tlb->nb_tlb - 1;
env->tlb->tlb_in_use = env->tlb->nb_tlb;
}
#endif /* CONFIG_USER_ONLY */
static void fpu_init (CPUMIPSState *env, const mips_def_t *def)
{
env->fpu = qemu_mallocz(sizeof(CPUMIPSFPUContext));
env->fpu->fcr0 = def->CP1_fcr0;
#ifdef CONFIG_USER_ONLY
if (env->CP0_Config1 & (1 << CP0C1_FP))
env->hflags |= MIPS_HFLAG_FPU;
if (env->user_mode_only) {
if (env->CP0_Config1 & (1 << CP0C1_FP))
env->hflags |= MIPS_HFLAG_FPU;
#ifdef TARGET_MIPS64
if (env->fpu->fcr0 & (1 << FCR0_F64))
env->hflags |= MIPS_HFLAG_F64;
#endif
if (env->fpu->fcr0 & (1 << FCR0_F64))
env->hflags |= MIPS_HFLAG_F64;
#endif
}
}
static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
@ -512,15 +510,15 @@ static void mvp_init (CPUMIPSState *env, const mips_def_t *def)
implemented, 5 TCs implemented. */
env->mvp->CP0_MVPConf0 = (1 << CP0MVPC0_M) | (1 << CP0MVPC0_TLBS) |
(0 << CP0MVPC0_GS) | (1 << CP0MVPC0_PCP) |
#ifndef CONFIG_USER_ONLY
/* Usermode has no TLB support */
(env->tlb->nb_tlb << CP0MVPC0_PTLBE) |
#endif
// TODO: actually do 2 VPEs.
// (1 << CP0MVPC0_TCA) | (0x1 << CP0MVPC0_PVPE) |
// (0x04 << CP0MVPC0_PTC);
(1 << CP0MVPC0_TCA) | (0x0 << CP0MVPC0_PVPE) |
(0x04 << CP0MVPC0_PTC);
/* Usermode has no TLB support */
if (!env->user_mode_only)
env->mvp->CP0_MVPConf0 |= (env->tlb->nb_tlb << CP0MVPC0_PTLBE);
/* Allocatable CP1 have media extensions, allocatable CP1 have FP support,
no UDI implemented, no CP2 implemented, 1 CP1 implemented. */
env->mvp->CP0_MVPConf1 = (1 << CP0MVPC1_CIM) | (1 << CP0MVPC1_CIF) |
@ -568,9 +566,8 @@ static int cpu_mips_register (CPUMIPSState *env, const mips_def_t *def)
env->CP0_SRSConf4 = def->CP0_SRSConf4;
env->insn_flags = def->insn_flags;
#ifndef CONFIG_USER_ONLY
mmu_init(env, def);
#endif
if (!env->user_mode_only)
mmu_init(env, def);
fpu_init(env, def);
mvp_init(env, def);
return 0;