mirror of https://gitee.com/openkylin/qemu.git
target-arm: Don't overuse CPUState
Scripted conversion: sed -i "s/CPUState/CPUARMState/g" target-arm/*.[hc] sed -i "s/#define CPUARMState/#define CPUState/" target-arm/cpu.h Signed-off-by: Andreas Färber <afaerber@suse.de> Acked-by: Anthony Liguori <aliguori@us.ibm.com> Acked-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Andreas Färber
parent
4d5712f19b
commit
0ecb72a588
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@ -461,13 +461,13 @@ void cpu_arm_set_cp_io(CPUARMState *env, int cpnum,
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#define MMU_MODE0_SUFFIX _kernel
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#define MMU_MODE1_SUFFIX _user
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#define MMU_USER_IDX 1
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static inline int cpu_mmu_index (CPUState *env)
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static inline int cpu_mmu_index (CPUARMState *env)
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{
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return (env->uncached_cpsr & CPSR_M) == ARM_CPU_MODE_USR ? 1 : 0;
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}
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#if defined(CONFIG_USER_ONLY)
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static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
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static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp)
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{
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if (newsp)
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env->regs[13] = newsp;
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@ -506,7 +506,7 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp)
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#define ARM_TBFLAG_CONDEXEC(F) \
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(((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT)
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static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
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static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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target_ulong *cs_base, int *flags)
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{
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int privmode;
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@ -529,7 +529,7 @@ static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc,
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}
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}
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static inline bool cpu_has_work(CPUState *env)
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static inline bool cpu_has_work(CPUARMState *env)
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{
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return env->interrupt_request &
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(CPU_INTERRUPT_FIQ | CPU_INTERRUPT_HARD | CPU_INTERRUPT_EXITTB);
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@ -537,7 +537,7 @@ static inline bool cpu_has_work(CPUState *env)
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#include "exec-all.h"
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static inline void cpu_pc_from_tb(CPUState *env, TranslationBlock *tb)
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static inline void cpu_pc_from_tb(CPUARMState *env, TranslationBlock *tb)
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{
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env->regs[15] = tb->pc;
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}
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@ -339,14 +339,14 @@ void cpu_state_reset(CPUARMState *env)
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set_float_detect_tininess(float_tininess_before_rounding,
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&env->vfp.standard_fp_status);
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tlb_flush(env, 1);
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/* Reset is a state change for some CPUState fields which we
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/* Reset is a state change for some CPUARMState fields which we
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* bake assumptions about into translated code, so we need to
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* tb_flush().
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*/
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tb_flush(env);
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}
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static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
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static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg)
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{
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int nregs;
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@ -373,7 +373,7 @@ static int vfp_gdb_get_reg(CPUState *env, uint8_t *buf, int reg)
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return 0;
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}
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static int vfp_gdb_set_reg(CPUState *env, uint8_t *buf, int reg)
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static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg)
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{
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int nregs;
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@ -498,7 +498,7 @@ void cpu_arm_close(CPUARMState *env)
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g_free(env);
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}
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static int bad_mode_switch(CPUState *env, int mode)
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static int bad_mode_switch(CPUARMState *env, int mode)
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{
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/* Return true if it is not valid for us to switch to
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* this CPU mode (ie all the UNPREDICTABLE cases in
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@ -628,12 +628,12 @@ uint32_t HELPER(abs)(uint32_t x)
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#if defined(CONFIG_USER_ONLY)
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void do_interrupt (CPUState *env)
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void do_interrupt (CPUARMState *env)
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{
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env->exception_index = -1;
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}
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int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address, int rw,
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int mmu_idx)
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{
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if (rw == 2) {
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@ -647,54 +647,54 @@ int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address, int rw,
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}
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/* These should probably raise undefined insn exceptions. */
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void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
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void HELPER(set_cp)(CPUARMState *env, uint32_t insn, uint32_t val)
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{
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int op1 = (insn >> 8) & 0xf;
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cpu_abort(env, "cp%i insn %08x\n", op1, insn);
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return;
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}
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uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
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uint32_t HELPER(get_cp)(CPUARMState *env, uint32_t insn)
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{
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int op1 = (insn >> 8) & 0xf;
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cpu_abort(env, "cp%i insn %08x\n", op1, insn);
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return 0;
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}
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void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
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void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
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{
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cpu_abort(env, "cp15 insn %08x\n", insn);
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}
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uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
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uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
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{
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cpu_abort(env, "cp15 insn %08x\n", insn);
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}
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/* These should probably raise undefined insn exceptions. */
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void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
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void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
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{
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cpu_abort(env, "v7m_mrs %d\n", reg);
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}
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uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
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uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
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{
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cpu_abort(env, "v7m_mrs %d\n", reg);
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return 0;
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}
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void switch_mode(CPUState *env, int mode)
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void switch_mode(CPUARMState *env, int mode)
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{
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if (mode != ARM_CPU_MODE_USR)
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cpu_abort(env, "Tried to switch out of user mode\n");
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}
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void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
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void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
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{
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cpu_abort(env, "banked r13 write\n");
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}
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uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
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uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
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{
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cpu_abort(env, "banked r13 read\n");
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return 0;
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@ -703,7 +703,7 @@ uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
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#else
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/* Map CPU modes onto saved register banks. */
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static inline int bank_number(CPUState *env, int mode)
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static inline int bank_number(CPUARMState *env, int mode)
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{
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switch (mode) {
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case ARM_CPU_MODE_USR:
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@ -724,7 +724,7 @@ static inline int bank_number(CPUState *env, int mode)
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return -1;
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}
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void switch_mode(CPUState *env, int mode)
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void switch_mode(CPUARMState *env, int mode)
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{
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int old_mode;
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int i;
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@ -997,7 +997,7 @@ void do_interrupt(CPUARMState *env)
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/* Check section/page access permissions.
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Returns the page protection flags, or zero if the access is not
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permitted. */
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static inline int check_ap(CPUState *env, int ap, int domain_prot,
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static inline int check_ap(CPUARMState *env, int ap, int domain_prot,
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int access_type, int is_user)
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{
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int prot_ro;
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@ -1047,7 +1047,7 @@ static inline int check_ap(CPUState *env, int ap, int domain_prot,
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}
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}
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static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
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static uint32_t get_level1_table_address(CPUARMState *env, uint32_t address)
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{
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uint32_t table;
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@ -1060,7 +1060,7 @@ static uint32_t get_level1_table_address(CPUState *env, uint32_t address)
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return table;
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}
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static int get_phys_addr_v5(CPUState *env, uint32_t address, int access_type,
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static int get_phys_addr_v5(CPUARMState *env, uint32_t address, int access_type,
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int is_user, uint32_t *phys_ptr, int *prot,
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target_ulong *page_size)
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{
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@ -1155,7 +1155,7 @@ do_fault:
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return code | (domain << 4);
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}
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static int get_phys_addr_v6(CPUState *env, uint32_t address, int access_type,
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static int get_phys_addr_v6(CPUARMState *env, uint32_t address, int access_type,
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int is_user, uint32_t *phys_ptr, int *prot,
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target_ulong *page_size)
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{
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@ -1259,7 +1259,7 @@ do_fault:
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return code | (domain << 4);
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}
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static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
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static int get_phys_addr_mpu(CPUARMState *env, uint32_t address, int access_type,
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int is_user, uint32_t *phys_ptr, int *prot)
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{
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int n;
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@ -1319,7 +1319,7 @@ static int get_phys_addr_mpu(CPUState *env, uint32_t address, int access_type,
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return 0;
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}
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static inline int get_phys_addr(CPUState *env, uint32_t address,
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static inline int get_phys_addr(CPUARMState *env, uint32_t address,
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int access_type, int is_user,
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uint32_t *phys_ptr, int *prot,
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target_ulong *page_size)
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@ -1347,7 +1347,7 @@ static inline int get_phys_addr(CPUState *env, uint32_t address,
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}
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}
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int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
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int cpu_arm_handle_mmu_fault (CPUARMState *env, target_ulong address,
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int access_type, int mmu_idx)
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{
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uint32_t phys_addr;
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@ -1380,7 +1380,7 @@ int cpu_arm_handle_mmu_fault (CPUState *env, target_ulong address,
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return 1;
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}
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target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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target_phys_addr_t cpu_get_phys_page_debug(CPUARMState *env, target_ulong addr)
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{
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uint32_t phys_addr;
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target_ulong page_size;
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@ -1395,7 +1395,7 @@ target_phys_addr_t cpu_get_phys_page_debug(CPUState *env, target_ulong addr)
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return phys_addr;
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}
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void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
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void HELPER(set_cp)(CPUARMState *env, uint32_t insn, uint32_t val)
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{
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int cp_num = (insn >> 8) & 0xf;
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int cp_info = (insn >> 5) & 7;
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@ -1407,7 +1407,7 @@ void HELPER(set_cp)(CPUState *env, uint32_t insn, uint32_t val)
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cp_info, src, operand, val);
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}
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uint32_t HELPER(get_cp)(CPUState *env, uint32_t insn)
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uint32_t HELPER(get_cp)(CPUARMState *env, uint32_t insn)
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{
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int cp_num = (insn >> 8) & 0xf;
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int cp_info = (insn >> 5) & 7;
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@ -1450,7 +1450,7 @@ static uint32_t extended_mpu_ap_bits(uint32_t val)
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return ret;
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}
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void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val)
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void HELPER(set_cp15)(CPUARMState *env, uint32_t insn, uint32_t val)
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{
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int op1;
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int op2;
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@ -1860,7 +1860,7 @@ bad_reg:
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(insn >> 16) & 0xf, crm, op1, op2);
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}
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uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn)
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uint32_t HELPER(get_cp15)(CPUARMState *env, uint32_t insn)
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{
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int op1;
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int op2;
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@ -2261,7 +2261,7 @@ bad_reg:
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return 0;
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}
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void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
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void HELPER(set_r13_banked)(CPUARMState *env, uint32_t mode, uint32_t val)
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{
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if ((env->uncached_cpsr & CPSR_M) == mode) {
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env->regs[13] = val;
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@ -2270,7 +2270,7 @@ void HELPER(set_r13_banked)(CPUState *env, uint32_t mode, uint32_t val)
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}
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}
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uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
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uint32_t HELPER(get_r13_banked)(CPUARMState *env, uint32_t mode)
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{
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if ((env->uncached_cpsr & CPSR_M) == mode) {
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return env->regs[13];
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@ -2279,7 +2279,7 @@ uint32_t HELPER(get_r13_banked)(CPUState *env, uint32_t mode)
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}
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}
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uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
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uint32_t HELPER(v7m_mrs)(CPUARMState *env, uint32_t reg)
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{
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switch (reg) {
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case 0: /* APSR */
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@ -2316,7 +2316,7 @@ uint32_t HELPER(v7m_mrs)(CPUState *env, uint32_t reg)
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}
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}
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void HELPER(v7m_msr)(CPUState *env, uint32_t reg, uint32_t val)
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void HELPER(v7m_msr)(CPUARMState *env, uint32_t reg, uint32_t val)
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{
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switch (reg) {
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case 0: /* APSR */
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@ -2672,7 +2672,7 @@ static inline int vfp_exceptbits_from_host(int host_bits)
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return target_bits;
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}
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uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
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uint32_t HELPER(vfp_get_fpscr)(CPUARMState *env)
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{
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int i;
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uint32_t fpscr;
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@ -2686,7 +2686,7 @@ uint32_t HELPER(vfp_get_fpscr)(CPUState *env)
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return fpscr;
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}
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uint32_t vfp_get_fpscr(CPUState *env)
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uint32_t vfp_get_fpscr(CPUARMState *env)
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{
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return HELPER(vfp_get_fpscr)(env);
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}
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@ -2711,7 +2711,7 @@ static inline int vfp_exceptbits_to_host(int target_bits)
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return host_bits;
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}
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void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
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void HELPER(vfp_set_fpscr)(CPUARMState *env, uint32_t val)
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{
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int i;
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uint32_t changed;
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@ -2752,7 +2752,7 @@ void HELPER(vfp_set_fpscr)(CPUState *env, uint32_t val)
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set_float_exception_flags(0, &env->vfp.standard_fp_status);
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}
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void vfp_set_fpscr(CPUState *env, uint32_t val)
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void vfp_set_fpscr(CPUARMState *env, uint32_t val)
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{
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HELPER(vfp_set_fpscr)(env, val);
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}
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@ -2796,19 +2796,19 @@ float64 VFP_HELPER(abs, d)(float64 a)
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return float64_abs(a);
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}
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float32 VFP_HELPER(sqrt, s)(float32 a, CPUState *env)
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float32 VFP_HELPER(sqrt, s)(float32 a, CPUARMState *env)
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{
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return float32_sqrt(a, &env->vfp.fp_status);
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}
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float64 VFP_HELPER(sqrt, d)(float64 a, CPUState *env)
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float64 VFP_HELPER(sqrt, d)(float64 a, CPUARMState *env)
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{
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return float64_sqrt(a, &env->vfp.fp_status);
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}
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/* XXX: check quiet/signaling case */
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#define DO_VFP_cmp(p, type) \
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void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
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void VFP_HELPER(cmp, p)(type a, type b, CPUARMState *env) \
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{ \
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uint32_t flags; \
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switch(type ## _compare_quiet(a, b, &env->vfp.fp_status)) { \
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@ -2820,7 +2820,7 @@ void VFP_HELPER(cmp, p)(type a, type b, CPUState *env) \
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env->vfp.xregs[ARM_VFP_FPSCR] = (flags << 28) \
|
||||
| (env->vfp.xregs[ARM_VFP_FPSCR] & 0x0fffffff); \
|
||||
} \
|
||||
void VFP_HELPER(cmpe, p)(type a, type b, CPUState *env) \
|
||||
void VFP_HELPER(cmpe, p)(type a, type b, CPUARMState *env) \
|
||||
{ \
|
||||
uint32_t flags; \
|
||||
switch(type ## _compare(a, b, &env->vfp.fp_status)) { \
|
||||
|
|
@ -2871,7 +2871,7 @@ FLOAT_CONVS(ui, d, 64, u)
|
|||
#undef FLOAT_CONVS
|
||||
|
||||
/* floating point conversion */
|
||||
float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
|
||||
float64 VFP_HELPER(fcvtd, s)(float32 x, CPUARMState *env)
|
||||
{
|
||||
float64 r = float32_to_float64(x, &env->vfp.fp_status);
|
||||
/* ARM requires that S<->D conversion of any kind of NaN generates
|
||||
|
|
@ -2880,7 +2880,7 @@ float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
|
|||
return float64_maybe_silence_nan(r);
|
||||
}
|
||||
|
||||
float32 VFP_HELPER(fcvts, d)(float64 x, CPUState *env)
|
||||
float32 VFP_HELPER(fcvts, d)(float64 x, CPUARMState *env)
|
||||
{
|
||||
float32 r = float64_to_float32(x, &env->vfp.fp_status);
|
||||
/* ARM requires that S<->D conversion of any kind of NaN generates
|
||||
|
|
@ -2923,7 +2923,7 @@ VFP_CONV_FIX(ul, s, 32, uint32, u)
|
|||
#undef VFP_CONV_FIX
|
||||
|
||||
/* Half precision conversions. */
|
||||
static float32 do_fcvt_f16_to_f32(uint32_t a, CPUState *env, float_status *s)
|
||||
static float32 do_fcvt_f16_to_f32(uint32_t a, CPUARMState *env, float_status *s)
|
||||
{
|
||||
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
|
||||
float32 r = float16_to_float32(make_float16(a), ieee, s);
|
||||
|
|
@ -2933,7 +2933,7 @@ static float32 do_fcvt_f16_to_f32(uint32_t a, CPUState *env, float_status *s)
|
|||
return r;
|
||||
}
|
||||
|
||||
static uint32_t do_fcvt_f32_to_f16(float32 a, CPUState *env, float_status *s)
|
||||
static uint32_t do_fcvt_f32_to_f16(float32 a, CPUARMState *env, float_status *s)
|
||||
{
|
||||
int ieee = (env->vfp.xregs[ARM_VFP_FPSCR] & (1 << 26)) == 0;
|
||||
float16 r = float32_to_float16(a, ieee, s);
|
||||
|
|
@ -2943,22 +2943,22 @@ static uint32_t do_fcvt_f32_to_f16(float32 a, CPUState *env, float_status *s)
|
|||
return float16_val(r);
|
||||
}
|
||||
|
||||
float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
|
||||
float32 HELPER(neon_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
|
||||
{
|
||||
return do_fcvt_f16_to_f32(a, env, &env->vfp.standard_fp_status);
|
||||
}
|
||||
|
||||
uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUState *env)
|
||||
uint32_t HELPER(neon_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
|
||||
{
|
||||
return do_fcvt_f32_to_f16(a, env, &env->vfp.standard_fp_status);
|
||||
}
|
||||
|
||||
float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUState *env)
|
||||
float32 HELPER(vfp_fcvt_f16_to_f32)(uint32_t a, CPUARMState *env)
|
||||
{
|
||||
return do_fcvt_f16_to_f32(a, env, &env->vfp.fp_status);
|
||||
}
|
||||
|
||||
uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env)
|
||||
uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUARMState *env)
|
||||
{
|
||||
return do_fcvt_f32_to_f16(a, env, &env->vfp.fp_status);
|
||||
}
|
||||
|
|
@ -2967,7 +2967,7 @@ uint32_t HELPER(vfp_fcvt_f32_to_f16)(float32 a, CPUState *env)
|
|||
#define float32_three make_float32(0x40400000)
|
||||
#define float32_one_point_five make_float32(0x3fc00000)
|
||||
|
||||
float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
|
||||
float32 HELPER(recps_f32)(float32 a, float32 b, CPUARMState *env)
|
||||
{
|
||||
float_status *s = &env->vfp.standard_fp_status;
|
||||
if ((float32_is_infinity(a) && float32_is_zero_or_denormal(b)) ||
|
||||
|
|
@ -2980,7 +2980,7 @@ float32 HELPER(recps_f32)(float32 a, float32 b, CPUState *env)
|
|||
return float32_sub(float32_two, float32_mul(a, b, s), s);
|
||||
}
|
||||
|
||||
float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
|
||||
float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUARMState *env)
|
||||
{
|
||||
float_status *s = &env->vfp.standard_fp_status;
|
||||
float32 product;
|
||||
|
|
@ -3005,7 +3005,7 @@ float32 HELPER(rsqrts_f32)(float32 a, float32 b, CPUState *env)
|
|||
/* The algorithm that must be used to calculate the estimate
|
||||
* is specified by the ARM ARM.
|
||||
*/
|
||||
static float64 recip_estimate(float64 a, CPUState *env)
|
||||
static float64 recip_estimate(float64 a, CPUARMState *env)
|
||||
{
|
||||
/* These calculations mustn't set any fp exception flags,
|
||||
* so we use a local copy of the fp_status.
|
||||
|
|
@ -3031,7 +3031,7 @@ static float64 recip_estimate(float64 a, CPUState *env)
|
|||
return float64_div(int64_to_float64(q_int, s), float64_256, s);
|
||||
}
|
||||
|
||||
float32 HELPER(recpe_f32)(float32 a, CPUState *env)
|
||||
float32 HELPER(recpe_f32)(float32 a, CPUARMState *env)
|
||||
{
|
||||
float_status *s = &env->vfp.standard_fp_status;
|
||||
float64 f64;
|
||||
|
|
@ -3075,7 +3075,7 @@ float32 HELPER(recpe_f32)(float32 a, CPUState *env)
|
|||
/* The algorithm that must be used to calculate the estimate
|
||||
* is specified by the ARM ARM.
|
||||
*/
|
||||
static float64 recip_sqrt_estimate(float64 a, CPUState *env)
|
||||
static float64 recip_sqrt_estimate(float64 a, CPUARMState *env)
|
||||
{
|
||||
/* These calculations mustn't set any fp exception flags,
|
||||
* so we use a local copy of the fp_status.
|
||||
|
|
@ -3127,7 +3127,7 @@ static float64 recip_sqrt_estimate(float64 a, CPUState *env)
|
|||
return float64_div(int64_to_float64(q_int, s), float64_256, s);
|
||||
}
|
||||
|
||||
float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
|
||||
float32 HELPER(rsqrte_f32)(float32 a, CPUARMState *env)
|
||||
{
|
||||
float_status *s = &env->vfp.standard_fp_status;
|
||||
int result_exp;
|
||||
|
|
@ -3178,7 +3178,7 @@ float32 HELPER(rsqrte_f32)(float32 a, CPUState *env)
|
|||
return make_float32(val);
|
||||
}
|
||||
|
||||
uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
|
||||
uint32_t HELPER(recpe_u32)(uint32_t a, CPUARMState *env)
|
||||
{
|
||||
float64 f64;
|
||||
|
||||
|
|
@ -3194,7 +3194,7 @@ uint32_t HELPER(recpe_u32)(uint32_t a, CPUState *env)
|
|||
return 0x80000000 | ((float64_val(f64) >> 21) & 0x7fffffff);
|
||||
}
|
||||
|
||||
uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUState *env)
|
||||
uint32_t HELPER(rsqrte_u32)(uint32_t a, CPUARMState *env)
|
||||
{
|
||||
float64 f64;
|
||||
|
||||
|
|
@ -3228,7 +3228,7 @@ float64 VFP_HELPER(muladd, d)(float64 a, float64 b, float64 c, void *fpstp)
|
|||
return float64_muladd(a, b, c, 0, fpst);
|
||||
}
|
||||
|
||||
void HELPER(set_teecr)(CPUState *env, uint32_t val)
|
||||
void HELPER(set_teecr)(CPUARMState *env, uint32_t val)
|
||||
{
|
||||
val &= 1;
|
||||
if (env->teecr != val) {
|
||||
|
|
|
|||
|
|
@ -162,7 +162,7 @@ uint64_t HELPER(iwmmxt_macuw)(uint64_t a, uint64_t b)
|
|||
SIMD64_SET(NBIT64(x), SIMD_NBIT) | \
|
||||
SIMD64_SET(ZBIT64(x), SIMD_ZBIT)
|
||||
#define IWMMXT_OP_UNPACK(S, SH0, SH1, SH2, SH3) \
|
||||
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, b)))(CPUState *env, \
|
||||
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, b)))(CPUARMState *env, \
|
||||
uint64_t a, uint64_t b) \
|
||||
{ \
|
||||
a = \
|
||||
|
|
@ -177,7 +177,7 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, b)))(CPUState *env, \
|
|||
NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7); \
|
||||
return a; \
|
||||
} \
|
||||
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, w)))(CPUState *env, \
|
||||
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, w)))(CPUARMState *env, \
|
||||
uint64_t a, uint64_t b) \
|
||||
{ \
|
||||
a = \
|
||||
|
|
@ -190,7 +190,7 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, w)))(CPUState *env, \
|
|||
NZBIT8(a >> 32, 2) | NZBIT8(a >> 48, 3); \
|
||||
return a; \
|
||||
} \
|
||||
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, l)))(CPUState *env, \
|
||||
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, l)))(CPUARMState *env, \
|
||||
uint64_t a, uint64_t b) \
|
||||
{ \
|
||||
a = \
|
||||
|
|
@ -200,7 +200,7 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, l)))(CPUState *env, \
|
|||
NZBIT32(a >> 0, 0) | NZBIT32(a >> 32, 1); \
|
||||
return a; \
|
||||
} \
|
||||
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ub)))(CPUState *env, \
|
||||
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ub)))(CPUARMState *env, \
|
||||
uint64_t x) \
|
||||
{ \
|
||||
x = \
|
||||
|
|
@ -213,7 +213,7 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ub)))(CPUState *env, \
|
|||
NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3); \
|
||||
return x; \
|
||||
} \
|
||||
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, uw)))(CPUState *env, \
|
||||
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, uw)))(CPUARMState *env, \
|
||||
uint64_t x) \
|
||||
{ \
|
||||
x = \
|
||||
|
|
@ -223,14 +223,14 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, uw)))(CPUState *env, \
|
|||
NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1); \
|
||||
return x; \
|
||||
} \
|
||||
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ul)))(CPUState *env, \
|
||||
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, ul)))(CPUARMState *env, \
|
||||
uint64_t x) \
|
||||
{ \
|
||||
x = (((x >> SH0) & 0xffffffff) << 0); \
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x >> 0); \
|
||||
return x; \
|
||||
} \
|
||||
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sb)))(CPUState *env, \
|
||||
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sb)))(CPUARMState *env, \
|
||||
uint64_t x) \
|
||||
{ \
|
||||
x = \
|
||||
|
|
@ -243,7 +243,7 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sb)))(CPUState *env, \
|
|||
NZBIT16(x >> 32, 2) | NZBIT16(x >> 48, 3); \
|
||||
return x; \
|
||||
} \
|
||||
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sw)))(CPUState *env, \
|
||||
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sw)))(CPUARMState *env, \
|
||||
uint64_t x) \
|
||||
{ \
|
||||
x = \
|
||||
|
|
@ -253,7 +253,7 @@ uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sw)))(CPUState *env, \
|
|||
NZBIT32(x >> 0, 0) | NZBIT32(x >> 32, 1); \
|
||||
return x; \
|
||||
} \
|
||||
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sl)))(CPUState *env, \
|
||||
uint64_t HELPER(glue(iwmmxt_unpack, glue(S, sl)))(CPUARMState *env, \
|
||||
uint64_t x) \
|
||||
{ \
|
||||
x = EXTEND32((x >> SH0) & 0xffffffff); \
|
||||
|
|
@ -264,7 +264,7 @@ IWMMXT_OP_UNPACK(l, 0, 8, 16, 24)
|
|||
IWMMXT_OP_UNPACK(h, 32, 40, 48, 56)
|
||||
|
||||
#define IWMMXT_OP_CMP(SUFF, Tb, Tw, Tl, O) \
|
||||
uint64_t HELPER(glue(iwmmxt_, glue(SUFF, b)))(CPUState *env, \
|
||||
uint64_t HELPER(glue(iwmmxt_, glue(SUFF, b)))(CPUARMState *env, \
|
||||
uint64_t a, uint64_t b) \
|
||||
{ \
|
||||
a = \
|
||||
|
|
@ -279,7 +279,7 @@ uint64_t HELPER(glue(iwmmxt_, glue(SUFF, b)))(CPUState *env, \
|
|||
NZBIT8(a >> 48, 6) | NZBIT8(a >> 56, 7); \
|
||||
return a; \
|
||||
} \
|
||||
uint64_t HELPER(glue(iwmmxt_, glue(SUFF, w)))(CPUState *env, \
|
||||
uint64_t HELPER(glue(iwmmxt_, glue(SUFF, w)))(CPUARMState *env, \
|
||||
uint64_t a, uint64_t b) \
|
||||
{ \
|
||||
a = CMP(0, Tw, O, 0xffff) | CMP(16, Tw, O, 0xffff) | \
|
||||
|
|
@ -289,7 +289,7 @@ uint64_t HELPER(glue(iwmmxt_, glue(SUFF, w)))(CPUState *env, \
|
|||
NZBIT16(a >> 32, 2) | NZBIT16(a >> 48, 3); \
|
||||
return a; \
|
||||
} \
|
||||
uint64_t HELPER(glue(iwmmxt_, glue(SUFF, l)))(CPUState *env, \
|
||||
uint64_t HELPER(glue(iwmmxt_, glue(SUFF, l)))(CPUARMState *env, \
|
||||
uint64_t a, uint64_t b) \
|
||||
{ \
|
||||
a = CMP(0, Tl, O, 0xffffffff) | \
|
||||
|
|
@ -329,7 +329,7 @@ IWMMXT_OP_CMP(adds, int8_t, int16_t, int32_t, +)
|
|||
#define AVGB(SHR) ((( \
|
||||
((a >> SHR) & 0xff) + ((b >> SHR) & 0xff) + round) >> 1) << SHR)
|
||||
#define IWMMXT_OP_AVGB(r) \
|
||||
uint64_t HELPER(iwmmxt_avgb##r)(CPUState *env, uint64_t a, uint64_t b) \
|
||||
uint64_t HELPER(iwmmxt_avgb##r)(CPUARMState *env, uint64_t a, uint64_t b) \
|
||||
{ \
|
||||
const int round = r; \
|
||||
a = AVGB(0) | AVGB(8) | AVGB(16) | AVGB(24) | \
|
||||
|
|
@ -353,7 +353,7 @@ IWMMXT_OP_AVGB(1)
|
|||
#define AVGW(SHR) ((( \
|
||||
((a >> SHR) & 0xffff) + ((b >> SHR) & 0xffff) + round) >> 1) << SHR)
|
||||
#define IWMMXT_OP_AVGW(r) \
|
||||
uint64_t HELPER(iwmmxt_avgw##r)(CPUState *env, uint64_t a, uint64_t b) \
|
||||
uint64_t HELPER(iwmmxt_avgw##r)(CPUARMState *env, uint64_t a, uint64_t b) \
|
||||
{ \
|
||||
const int round = r; \
|
||||
a = AVGW(0) | AVGW(16) | AVGW(32) | AVGW(48); \
|
||||
|
|
@ -464,7 +464,7 @@ uint32_t HELPER(iwmmxt_msbl)(uint64_t x)
|
|||
}
|
||||
|
||||
/* FIXME: Split wCASF setting into a separate op to avoid env use. */
|
||||
uint64_t HELPER(iwmmxt_srlw)(CPUState *env, uint64_t x, uint32_t n)
|
||||
uint64_t HELPER(iwmmxt_srlw)(CPUARMState *env, uint64_t x, uint32_t n)
|
||||
{
|
||||
x = (((x & (0xffffll << 0)) >> n) & (0xffffll << 0)) |
|
||||
(((x & (0xffffll << 16)) >> n) & (0xffffll << 16)) |
|
||||
|
|
@ -476,7 +476,7 @@ uint64_t HELPER(iwmmxt_srlw)(CPUState *env, uint64_t x, uint32_t n)
|
|||
return x;
|
||||
}
|
||||
|
||||
uint64_t HELPER(iwmmxt_srll)(CPUState *env, uint64_t x, uint32_t n)
|
||||
uint64_t HELPER(iwmmxt_srll)(CPUARMState *env, uint64_t x, uint32_t n)
|
||||
{
|
||||
x = ((x & (0xffffffffll << 0)) >> n) |
|
||||
((x >> n) & (0xffffffffll << 32));
|
||||
|
|
@ -485,14 +485,14 @@ uint64_t HELPER(iwmmxt_srll)(CPUState *env, uint64_t x, uint32_t n)
|
|||
return x;
|
||||
}
|
||||
|
||||
uint64_t HELPER(iwmmxt_srlq)(CPUState *env, uint64_t x, uint32_t n)
|
||||
uint64_t HELPER(iwmmxt_srlq)(CPUARMState *env, uint64_t x, uint32_t n)
|
||||
{
|
||||
x >>= n;
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
|
||||
return x;
|
||||
}
|
||||
|
||||
uint64_t HELPER(iwmmxt_sllw)(CPUState *env, uint64_t x, uint32_t n)
|
||||
uint64_t HELPER(iwmmxt_sllw)(CPUARMState *env, uint64_t x, uint32_t n)
|
||||
{
|
||||
x = (((x & (0xffffll << 0)) << n) & (0xffffll << 0)) |
|
||||
(((x & (0xffffll << 16)) << n) & (0xffffll << 16)) |
|
||||
|
|
@ -504,7 +504,7 @@ uint64_t HELPER(iwmmxt_sllw)(CPUState *env, uint64_t x, uint32_t n)
|
|||
return x;
|
||||
}
|
||||
|
||||
uint64_t HELPER(iwmmxt_slll)(CPUState *env, uint64_t x, uint32_t n)
|
||||
uint64_t HELPER(iwmmxt_slll)(CPUARMState *env, uint64_t x, uint32_t n)
|
||||
{
|
||||
x = ((x << n) & (0xffffffffll << 0)) |
|
||||
((x & (0xffffffffll << 32)) << n);
|
||||
|
|
@ -513,14 +513,14 @@ uint64_t HELPER(iwmmxt_slll)(CPUState *env, uint64_t x, uint32_t n)
|
|||
return x;
|
||||
}
|
||||
|
||||
uint64_t HELPER(iwmmxt_sllq)(CPUState *env, uint64_t x, uint32_t n)
|
||||
uint64_t HELPER(iwmmxt_sllq)(CPUARMState *env, uint64_t x, uint32_t n)
|
||||
{
|
||||
x <<= n;
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
|
||||
return x;
|
||||
}
|
||||
|
||||
uint64_t HELPER(iwmmxt_sraw)(CPUState *env, uint64_t x, uint32_t n)
|
||||
uint64_t HELPER(iwmmxt_sraw)(CPUARMState *env, uint64_t x, uint32_t n)
|
||||
{
|
||||
x = ((uint64_t) ((EXTEND16(x >> 0) >> n) & 0xffff) << 0) |
|
||||
((uint64_t) ((EXTEND16(x >> 16) >> n) & 0xffff) << 16) |
|
||||
|
|
@ -532,7 +532,7 @@ uint64_t HELPER(iwmmxt_sraw)(CPUState *env, uint64_t x, uint32_t n)
|
|||
return x;
|
||||
}
|
||||
|
||||
uint64_t HELPER(iwmmxt_sral)(CPUState *env, uint64_t x, uint32_t n)
|
||||
uint64_t HELPER(iwmmxt_sral)(CPUARMState *env, uint64_t x, uint32_t n)
|
||||
{
|
||||
x = (((EXTEND32(x >> 0) >> n) & 0xffffffff) << 0) |
|
||||
(((EXTEND32(x >> 32) >> n) & 0xffffffff) << 32);
|
||||
|
|
@ -541,14 +541,14 @@ uint64_t HELPER(iwmmxt_sral)(CPUState *env, uint64_t x, uint32_t n)
|
|||
return x;
|
||||
}
|
||||
|
||||
uint64_t HELPER(iwmmxt_sraq)(CPUState *env, uint64_t x, uint32_t n)
|
||||
uint64_t HELPER(iwmmxt_sraq)(CPUARMState *env, uint64_t x, uint32_t n)
|
||||
{
|
||||
x = (int64_t) x >> n;
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
|
||||
return x;
|
||||
}
|
||||
|
||||
uint64_t HELPER(iwmmxt_rorw)(CPUState *env, uint64_t x, uint32_t n)
|
||||
uint64_t HELPER(iwmmxt_rorw)(CPUARMState *env, uint64_t x, uint32_t n)
|
||||
{
|
||||
x = ((((x & (0xffffll << 0)) >> n) |
|
||||
((x & (0xffffll << 0)) << (16 - n))) & (0xffffll << 0)) |
|
||||
|
|
@ -564,7 +564,7 @@ uint64_t HELPER(iwmmxt_rorw)(CPUState *env, uint64_t x, uint32_t n)
|
|||
return x;
|
||||
}
|
||||
|
||||
uint64_t HELPER(iwmmxt_rorl)(CPUState *env, uint64_t x, uint32_t n)
|
||||
uint64_t HELPER(iwmmxt_rorl)(CPUARMState *env, uint64_t x, uint32_t n)
|
||||
{
|
||||
x = ((x & (0xffffffffll << 0)) >> n) |
|
||||
((x >> n) & (0xffffffffll << 32)) |
|
||||
|
|
@ -575,14 +575,14 @@ uint64_t HELPER(iwmmxt_rorl)(CPUState *env, uint64_t x, uint32_t n)
|
|||
return x;
|
||||
}
|
||||
|
||||
uint64_t HELPER(iwmmxt_rorq)(CPUState *env, uint64_t x, uint32_t n)
|
||||
uint64_t HELPER(iwmmxt_rorq)(CPUARMState *env, uint64_t x, uint32_t n)
|
||||
{
|
||||
x = (x >> n) | (x << (64 - n));
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] = NZBIT64(x);
|
||||
return x;
|
||||
}
|
||||
|
||||
uint64_t HELPER(iwmmxt_shufh)(CPUState *env, uint64_t x, uint32_t n)
|
||||
uint64_t HELPER(iwmmxt_shufh)(CPUARMState *env, uint64_t x, uint32_t n)
|
||||
{
|
||||
x = (((x >> ((n << 4) & 0x30)) & 0xffff) << 0) |
|
||||
(((x >> ((n << 2) & 0x30)) & 0xffff) << 16) |
|
||||
|
|
@ -595,7 +595,7 @@ uint64_t HELPER(iwmmxt_shufh)(CPUState *env, uint64_t x, uint32_t n)
|
|||
}
|
||||
|
||||
/* TODO: Unsigned-Saturation */
|
||||
uint64_t HELPER(iwmmxt_packuw)(CPUState *env, uint64_t a, uint64_t b)
|
||||
uint64_t HELPER(iwmmxt_packuw)(CPUARMState *env, uint64_t a, uint64_t b)
|
||||
{
|
||||
a = (((a >> 0) & 0xff) << 0) | (((a >> 16) & 0xff) << 8) |
|
||||
(((a >> 32) & 0xff) << 16) | (((a >> 48) & 0xff) << 24) |
|
||||
|
|
@ -609,7 +609,7 @@ uint64_t HELPER(iwmmxt_packuw)(CPUState *env, uint64_t a, uint64_t b)
|
|||
return a;
|
||||
}
|
||||
|
||||
uint64_t HELPER(iwmmxt_packul)(CPUState *env, uint64_t a, uint64_t b)
|
||||
uint64_t HELPER(iwmmxt_packul)(CPUARMState *env, uint64_t a, uint64_t b)
|
||||
{
|
||||
a = (((a >> 0) & 0xffff) << 0) | (((a >> 32) & 0xffff) << 16) |
|
||||
(((b >> 0) & 0xffff) << 32) | (((b >> 32) & 0xffff) << 48);
|
||||
|
|
@ -619,7 +619,7 @@ uint64_t HELPER(iwmmxt_packul)(CPUState *env, uint64_t a, uint64_t b)
|
|||
return a;
|
||||
}
|
||||
|
||||
uint64_t HELPER(iwmmxt_packuq)(CPUState *env, uint64_t a, uint64_t b)
|
||||
uint64_t HELPER(iwmmxt_packuq)(CPUARMState *env, uint64_t a, uint64_t b)
|
||||
{
|
||||
a = (a & 0xffffffff) | ((b & 0xffffffff) << 32);
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
|
||||
|
|
@ -628,7 +628,7 @@ uint64_t HELPER(iwmmxt_packuq)(CPUState *env, uint64_t a, uint64_t b)
|
|||
}
|
||||
|
||||
/* TODO: Signed-Saturation */
|
||||
uint64_t HELPER(iwmmxt_packsw)(CPUState *env, uint64_t a, uint64_t b)
|
||||
uint64_t HELPER(iwmmxt_packsw)(CPUARMState *env, uint64_t a, uint64_t b)
|
||||
{
|
||||
a = (((a >> 0) & 0xff) << 0) | (((a >> 16) & 0xff) << 8) |
|
||||
(((a >> 32) & 0xff) << 16) | (((a >> 48) & 0xff) << 24) |
|
||||
|
|
@ -642,7 +642,7 @@ uint64_t HELPER(iwmmxt_packsw)(CPUState *env, uint64_t a, uint64_t b)
|
|||
return a;
|
||||
}
|
||||
|
||||
uint64_t HELPER(iwmmxt_packsl)(CPUState *env, uint64_t a, uint64_t b)
|
||||
uint64_t HELPER(iwmmxt_packsl)(CPUARMState *env, uint64_t a, uint64_t b)
|
||||
{
|
||||
a = (((a >> 0) & 0xffff) << 0) | (((a >> 32) & 0xffff) << 16) |
|
||||
(((b >> 0) & 0xffff) << 32) | (((b >> 32) & 0xffff) << 48);
|
||||
|
|
@ -652,7 +652,7 @@ uint64_t HELPER(iwmmxt_packsl)(CPUState *env, uint64_t a, uint64_t b)
|
|||
return a;
|
||||
}
|
||||
|
||||
uint64_t HELPER(iwmmxt_packsq)(CPUState *env, uint64_t a, uint64_t b)
|
||||
uint64_t HELPER(iwmmxt_packsq)(CPUARMState *env, uint64_t a, uint64_t b)
|
||||
{
|
||||
a = (a & 0xffffffff) | ((b & 0xffffffff) << 32);
|
||||
env->iwmmxt.cregs[ARM_IWMMXT_wCASF] =
|
||||
|
|
|
|||
|
|
@ -114,7 +114,7 @@ uint32_t HELPER(glue(neon_,name))(uint32_t arg1, uint32_t arg2) \
|
|||
NEON_VOP_BODY(vtype, n)
|
||||
|
||||
#define NEON_VOP_ENV(name, vtype, n) \
|
||||
uint32_t HELPER(glue(neon_,name))(CPUState *env, uint32_t arg1, uint32_t arg2) \
|
||||
uint32_t HELPER(glue(neon_,name))(CPUARMState *env, uint32_t arg1, uint32_t arg2) \
|
||||
NEON_VOP_BODY(vtype, n)
|
||||
|
||||
/* Pairwise operations. */
|
||||
|
|
@ -172,7 +172,7 @@ NEON_VOP_ENV(qadd_u16, neon_u16, 2)
|
|||
#undef NEON_FN
|
||||
#undef NEON_USAT
|
||||
|
||||
uint32_t HELPER(neon_qadd_u32)(CPUState *env, uint32_t a, uint32_t b)
|
||||
uint32_t HELPER(neon_qadd_u32)(CPUARMState *env, uint32_t a, uint32_t b)
|
||||
{
|
||||
uint32_t res = a + b;
|
||||
if (res < a) {
|
||||
|
|
@ -182,7 +182,7 @@ uint32_t HELPER(neon_qadd_u32)(CPUState *env, uint32_t a, uint32_t b)
|
|||
return res;
|
||||
}
|
||||
|
||||
uint64_t HELPER(neon_qadd_u64)(CPUState *env, uint64_t src1, uint64_t src2)
|
||||
uint64_t HELPER(neon_qadd_u64)(CPUARMState *env, uint64_t src1, uint64_t src2)
|
||||
{
|
||||
uint64_t res;
|
||||
|
||||
|
|
@ -214,7 +214,7 @@ NEON_VOP_ENV(qadd_s16, neon_s16, 2)
|
|||
#undef NEON_FN
|
||||
#undef NEON_SSAT
|
||||
|
||||
uint32_t HELPER(neon_qadd_s32)(CPUState *env, uint32_t a, uint32_t b)
|
||||
uint32_t HELPER(neon_qadd_s32)(CPUARMState *env, uint32_t a, uint32_t b)
|
||||
{
|
||||
uint32_t res = a + b;
|
||||
if (((res ^ a) & SIGNBIT) && !((a ^ b) & SIGNBIT)) {
|
||||
|
|
@ -224,7 +224,7 @@ uint32_t HELPER(neon_qadd_s32)(CPUState *env, uint32_t a, uint32_t b)
|
|||
return res;
|
||||
}
|
||||
|
||||
uint64_t HELPER(neon_qadd_s64)(CPUState *env, uint64_t src1, uint64_t src2)
|
||||
uint64_t HELPER(neon_qadd_s64)(CPUARMState *env, uint64_t src1, uint64_t src2)
|
||||
{
|
||||
uint64_t res;
|
||||
|
||||
|
|
@ -252,7 +252,7 @@ NEON_VOP_ENV(qsub_u16, neon_u16, 2)
|
|||
#undef NEON_FN
|
||||
#undef NEON_USAT
|
||||
|
||||
uint32_t HELPER(neon_qsub_u32)(CPUState *env, uint32_t a, uint32_t b)
|
||||
uint32_t HELPER(neon_qsub_u32)(CPUARMState *env, uint32_t a, uint32_t b)
|
||||
{
|
||||
uint32_t res = a - b;
|
||||
if (res > a) {
|
||||
|
|
@ -262,7 +262,7 @@ uint32_t HELPER(neon_qsub_u32)(CPUState *env, uint32_t a, uint32_t b)
|
|||
return res;
|
||||
}
|
||||
|
||||
uint64_t HELPER(neon_qsub_u64)(CPUState *env, uint64_t src1, uint64_t src2)
|
||||
uint64_t HELPER(neon_qsub_u64)(CPUARMState *env, uint64_t src1, uint64_t src2)
|
||||
{
|
||||
uint64_t res;
|
||||
|
||||
|
|
@ -295,7 +295,7 @@ NEON_VOP_ENV(qsub_s16, neon_s16, 2)
|
|||
#undef NEON_FN
|
||||
#undef NEON_SSAT
|
||||
|
||||
uint32_t HELPER(neon_qsub_s32)(CPUState *env, uint32_t a, uint32_t b)
|
||||
uint32_t HELPER(neon_qsub_s32)(CPUARMState *env, uint32_t a, uint32_t b)
|
||||
{
|
||||
uint32_t res = a - b;
|
||||
if (((res ^ a) & SIGNBIT) && ((a ^ b) & SIGNBIT)) {
|
||||
|
|
@ -305,7 +305,7 @@ uint32_t HELPER(neon_qsub_s32)(CPUState *env, uint32_t a, uint32_t b)
|
|||
return res;
|
||||
}
|
||||
|
||||
uint64_t HELPER(neon_qsub_s64)(CPUState *env, uint64_t src1, uint64_t src2)
|
||||
uint64_t HELPER(neon_qsub_s64)(CPUARMState *env, uint64_t src1, uint64_t src2)
|
||||
{
|
||||
uint64_t res;
|
||||
|
||||
|
|
@ -661,7 +661,7 @@ NEON_VOP_ENV(qshl_u16, neon_u16, 2)
|
|||
NEON_VOP_ENV(qshl_u32, neon_u32, 1)
|
||||
#undef NEON_FN
|
||||
|
||||
uint64_t HELPER(neon_qshl_u64)(CPUState *env, uint64_t val, uint64_t shiftop)
|
||||
uint64_t HELPER(neon_qshl_u64)(CPUARMState *env, uint64_t val, uint64_t shiftop)
|
||||
{
|
||||
int8_t shift = (int8_t)shiftop;
|
||||
if (shift >= 64) {
|
||||
|
|
@ -716,7 +716,7 @@ NEON_VOP_ENV(qshl_s16, neon_s16, 2)
|
|||
NEON_VOP_ENV(qshl_s32, neon_s32, 1)
|
||||
#undef NEON_FN
|
||||
|
||||
uint64_t HELPER(neon_qshl_s64)(CPUState *env, uint64_t valop, uint64_t shiftop)
|
||||
uint64_t HELPER(neon_qshl_s64)(CPUARMState *env, uint64_t valop, uint64_t shiftop)
|
||||
{
|
||||
int8_t shift = (uint8_t)shiftop;
|
||||
int64_t val = valop;
|
||||
|
|
@ -770,7 +770,7 @@ NEON_VOP_ENV(qshlu_s8, neon_u8, 4)
|
|||
NEON_VOP_ENV(qshlu_s16, neon_u16, 2)
|
||||
#undef NEON_FN
|
||||
|
||||
uint32_t HELPER(neon_qshlu_s32)(CPUState *env, uint32_t valop, uint32_t shiftop)
|
||||
uint32_t HELPER(neon_qshlu_s32)(CPUARMState *env, uint32_t valop, uint32_t shiftop)
|
||||
{
|
||||
if ((int32_t)valop < 0) {
|
||||
SET_QC();
|
||||
|
|
@ -779,7 +779,7 @@ uint32_t HELPER(neon_qshlu_s32)(CPUState *env, uint32_t valop, uint32_t shiftop)
|
|||
return helper_neon_qshl_u32(env, valop, shiftop);
|
||||
}
|
||||
|
||||
uint64_t HELPER(neon_qshlu_s64)(CPUState *env, uint64_t valop, uint64_t shiftop)
|
||||
uint64_t HELPER(neon_qshlu_s64)(CPUARMState *env, uint64_t valop, uint64_t shiftop)
|
||||
{
|
||||
if ((int64_t)valop < 0) {
|
||||
SET_QC();
|
||||
|
|
@ -818,7 +818,7 @@ NEON_VOP_ENV(qrshl_u16, neon_u16, 2)
|
|||
|
||||
/* The addition of the rounding constant may overflow, so we use an
|
||||
* intermediate 64 bits accumulator. */
|
||||
uint32_t HELPER(neon_qrshl_u32)(CPUState *env, uint32_t val, uint32_t shiftop)
|
||||
uint32_t HELPER(neon_qrshl_u32)(CPUARMState *env, uint32_t val, uint32_t shiftop)
|
||||
{
|
||||
uint32_t dest;
|
||||
int8_t shift = (int8_t)shiftop;
|
||||
|
|
@ -848,7 +848,7 @@ uint32_t HELPER(neon_qrshl_u32)(CPUState *env, uint32_t val, uint32_t shiftop)
|
|||
|
||||
/* Handling addition overflow with 64 bits inputs values is more
|
||||
* tricky than with 32 bits values. */
|
||||
uint64_t HELPER(neon_qrshl_u64)(CPUState *env, uint64_t val, uint64_t shiftop)
|
||||
uint64_t HELPER(neon_qrshl_u64)(CPUARMState *env, uint64_t val, uint64_t shiftop)
|
||||
{
|
||||
int8_t shift = (int8_t)shiftop;
|
||||
if (shift >= 64) {
|
||||
|
|
@ -915,7 +915,7 @@ NEON_VOP_ENV(qrshl_s16, neon_s16, 2)
|
|||
|
||||
/* The addition of the rounding constant may overflow, so we use an
|
||||
* intermediate 64 bits accumulator. */
|
||||
uint32_t HELPER(neon_qrshl_s32)(CPUState *env, uint32_t valop, uint32_t shiftop)
|
||||
uint32_t HELPER(neon_qrshl_s32)(CPUARMState *env, uint32_t valop, uint32_t shiftop)
|
||||
{
|
||||
int32_t dest;
|
||||
int32_t val = (int32_t)valop;
|
||||
|
|
@ -944,7 +944,7 @@ uint32_t HELPER(neon_qrshl_s32)(CPUState *env, uint32_t valop, uint32_t shiftop)
|
|||
|
||||
/* Handling addition overflow with 64 bits inputs values is more
|
||||
* tricky than with 32 bits values. */
|
||||
uint64_t HELPER(neon_qrshl_s64)(CPUState *env, uint64_t valop, uint64_t shiftop)
|
||||
uint64_t HELPER(neon_qrshl_s64)(CPUARMState *env, uint64_t valop, uint64_t shiftop)
|
||||
{
|
||||
int8_t shift = (uint8_t)shiftop;
|
||||
int64_t val = valop;
|
||||
|
|
@ -1223,7 +1223,7 @@ uint32_t HELPER(neon_narrow_round_high_u16)(uint64_t x)
|
|||
return ((x >> 16) & 0xffff) | ((x >> 32) & 0xffff0000);
|
||||
}
|
||||
|
||||
uint32_t HELPER(neon_unarrow_sat8)(CPUState *env, uint64_t x)
|
||||
uint32_t HELPER(neon_unarrow_sat8)(CPUARMState *env, uint64_t x)
|
||||
{
|
||||
uint16_t s;
|
||||
uint8_t d;
|
||||
|
|
@ -1250,7 +1250,7 @@ uint32_t HELPER(neon_unarrow_sat8)(CPUState *env, uint64_t x)
|
|||
return res;
|
||||
}
|
||||
|
||||
uint32_t HELPER(neon_narrow_sat_u8)(CPUState *env, uint64_t x)
|
||||
uint32_t HELPER(neon_narrow_sat_u8)(CPUARMState *env, uint64_t x)
|
||||
{
|
||||
uint16_t s;
|
||||
uint8_t d;
|
||||
|
|
@ -1273,7 +1273,7 @@ uint32_t HELPER(neon_narrow_sat_u8)(CPUState *env, uint64_t x)
|
|||
return res;
|
||||
}
|
||||
|
||||
uint32_t HELPER(neon_narrow_sat_s8)(CPUState *env, uint64_t x)
|
||||
uint32_t HELPER(neon_narrow_sat_s8)(CPUARMState *env, uint64_t x)
|
||||
{
|
||||
int16_t s;
|
||||
uint8_t d;
|
||||
|
|
@ -1296,7 +1296,7 @@ uint32_t HELPER(neon_narrow_sat_s8)(CPUState *env, uint64_t x)
|
|||
return res;
|
||||
}
|
||||
|
||||
uint32_t HELPER(neon_unarrow_sat16)(CPUState *env, uint64_t x)
|
||||
uint32_t HELPER(neon_unarrow_sat16)(CPUARMState *env, uint64_t x)
|
||||
{
|
||||
uint32_t high;
|
||||
uint32_t low;
|
||||
|
|
@ -1319,7 +1319,7 @@ uint32_t HELPER(neon_unarrow_sat16)(CPUState *env, uint64_t x)
|
|||
return low | (high << 16);
|
||||
}
|
||||
|
||||
uint32_t HELPER(neon_narrow_sat_u16)(CPUState *env, uint64_t x)
|
||||
uint32_t HELPER(neon_narrow_sat_u16)(CPUARMState *env, uint64_t x)
|
||||
{
|
||||
uint32_t high;
|
||||
uint32_t low;
|
||||
|
|
@ -1336,7 +1336,7 @@ uint32_t HELPER(neon_narrow_sat_u16)(CPUState *env, uint64_t x)
|
|||
return low | (high << 16);
|
||||
}
|
||||
|
||||
uint32_t HELPER(neon_narrow_sat_s16)(CPUState *env, uint64_t x)
|
||||
uint32_t HELPER(neon_narrow_sat_s16)(CPUARMState *env, uint64_t x)
|
||||
{
|
||||
int32_t low;
|
||||
int32_t high;
|
||||
|
|
@ -1353,7 +1353,7 @@ uint32_t HELPER(neon_narrow_sat_s16)(CPUState *env, uint64_t x)
|
|||
return (uint16_t)low | (high << 16);
|
||||
}
|
||||
|
||||
uint32_t HELPER(neon_unarrow_sat32)(CPUState *env, uint64_t x)
|
||||
uint32_t HELPER(neon_unarrow_sat32)(CPUARMState *env, uint64_t x)
|
||||
{
|
||||
if (x & 0x8000000000000000ull) {
|
||||
SET_QC();
|
||||
|
|
@ -1366,7 +1366,7 @@ uint32_t HELPER(neon_unarrow_sat32)(CPUState *env, uint64_t x)
|
|||
return x;
|
||||
}
|
||||
|
||||
uint32_t HELPER(neon_narrow_sat_u32)(CPUState *env, uint64_t x)
|
||||
uint32_t HELPER(neon_narrow_sat_u32)(CPUARMState *env, uint64_t x)
|
||||
{
|
||||
if (x > 0xffffffffu) {
|
||||
SET_QC();
|
||||
|
|
@ -1375,7 +1375,7 @@ uint32_t HELPER(neon_narrow_sat_u32)(CPUState *env, uint64_t x)
|
|||
return x;
|
||||
}
|
||||
|
||||
uint32_t HELPER(neon_narrow_sat_s32)(CPUState *env, uint64_t x)
|
||||
uint32_t HELPER(neon_narrow_sat_s32)(CPUARMState *env, uint64_t x)
|
||||
{
|
||||
if ((int64_t)x != (int32_t)x) {
|
||||
SET_QC();
|
||||
|
|
@ -1482,7 +1482,7 @@ uint64_t HELPER(neon_subl_u32)(uint64_t a, uint64_t b)
|
|||
return (a - b) ^ mask;
|
||||
}
|
||||
|
||||
uint64_t HELPER(neon_addl_saturate_s32)(CPUState *env, uint64_t a, uint64_t b)
|
||||
uint64_t HELPER(neon_addl_saturate_s32)(CPUARMState *env, uint64_t a, uint64_t b)
|
||||
{
|
||||
uint32_t x, y;
|
||||
uint32_t low, high;
|
||||
|
|
@ -1504,7 +1504,7 @@ uint64_t HELPER(neon_addl_saturate_s32)(CPUState *env, uint64_t a, uint64_t b)
|
|||
return low | ((uint64_t)high << 32);
|
||||
}
|
||||
|
||||
uint64_t HELPER(neon_addl_saturate_s64)(CPUState *env, uint64_t a, uint64_t b)
|
||||
uint64_t HELPER(neon_addl_saturate_s64)(CPUARMState *env, uint64_t a, uint64_t b)
|
||||
{
|
||||
uint64_t result;
|
||||
|
||||
|
|
@ -1680,7 +1680,7 @@ uint64_t HELPER(neon_negl_u64)(uint64_t x)
|
|||
} else if (x < 0) { \
|
||||
x = -x; \
|
||||
}} while (0)
|
||||
uint32_t HELPER(neon_qabs_s8)(CPUState *env, uint32_t x)
|
||||
uint32_t HELPER(neon_qabs_s8)(CPUARMState *env, uint32_t x)
|
||||
{
|
||||
neon_s8 vec;
|
||||
NEON_UNPACK(neon_s8, vec, x);
|
||||
|
|
@ -1700,7 +1700,7 @@ uint32_t HELPER(neon_qabs_s8)(CPUState *env, uint32_t x)
|
|||
} else { \
|
||||
x = -x; \
|
||||
}} while (0)
|
||||
uint32_t HELPER(neon_qneg_s8)(CPUState *env, uint32_t x)
|
||||
uint32_t HELPER(neon_qneg_s8)(CPUARMState *env, uint32_t x)
|
||||
{
|
||||
neon_s8 vec;
|
||||
NEON_UNPACK(neon_s8, vec, x);
|
||||
|
|
@ -1720,7 +1720,7 @@ uint32_t HELPER(neon_qneg_s8)(CPUState *env, uint32_t x)
|
|||
} else if (x < 0) { \
|
||||
x = -x; \
|
||||
}} while (0)
|
||||
uint32_t HELPER(neon_qabs_s16)(CPUState *env, uint32_t x)
|
||||
uint32_t HELPER(neon_qabs_s16)(CPUARMState *env, uint32_t x)
|
||||
{
|
||||
neon_s16 vec;
|
||||
NEON_UNPACK(neon_s16, vec, x);
|
||||
|
|
@ -1738,7 +1738,7 @@ uint32_t HELPER(neon_qabs_s16)(CPUState *env, uint32_t x)
|
|||
} else { \
|
||||
x = -x; \
|
||||
}} while (0)
|
||||
uint32_t HELPER(neon_qneg_s16)(CPUState *env, uint32_t x)
|
||||
uint32_t HELPER(neon_qneg_s16)(CPUARMState *env, uint32_t x)
|
||||
{
|
||||
neon_s16 vec;
|
||||
NEON_UNPACK(neon_s16, vec, x);
|
||||
|
|
@ -1749,7 +1749,7 @@ uint32_t HELPER(neon_qneg_s16)(CPUState *env, uint32_t x)
|
|||
}
|
||||
#undef DO_QNEG16
|
||||
|
||||
uint32_t HELPER(neon_qabs_s32)(CPUState *env, uint32_t x)
|
||||
uint32_t HELPER(neon_qabs_s32)(CPUARMState *env, uint32_t x)
|
||||
{
|
||||
if (x == SIGNBIT) {
|
||||
SET_QC();
|
||||
|
|
@ -1760,7 +1760,7 @@ uint32_t HELPER(neon_qabs_s32)(CPUState *env, uint32_t x)
|
|||
return x;
|
||||
}
|
||||
|
||||
uint32_t HELPER(neon_qneg_s32)(CPUState *env, uint32_t x)
|
||||
uint32_t HELPER(neon_qneg_s32)(CPUARMState *env, uint32_t x)
|
||||
{
|
||||
if (x == SIGNBIT) {
|
||||
SET_QC();
|
||||
|
|
@ -1832,7 +1832,7 @@ uint32_t HELPER(neon_acgt_f32)(uint32_t a, uint32_t b, void *fpstp)
|
|||
|
||||
#define ELEM(V, N, SIZE) (((V) >> ((N) * (SIZE))) & ((1ull << (SIZE)) - 1))
|
||||
|
||||
void HELPER(neon_qunzip8)(CPUState *env, uint32_t rd, uint32_t rm)
|
||||
void HELPER(neon_qunzip8)(CPUARMState *env, uint32_t rd, uint32_t rm)
|
||||
{
|
||||
uint64_t zm0 = float64_val(env->vfp.regs[rm]);
|
||||
uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]);
|
||||
|
|
@ -1860,7 +1860,7 @@ void HELPER(neon_qunzip8)(CPUState *env, uint32_t rd, uint32_t rm)
|
|||
env->vfp.regs[rd + 1] = make_float64(d1);
|
||||
}
|
||||
|
||||
void HELPER(neon_qunzip16)(CPUState *env, uint32_t rd, uint32_t rm)
|
||||
void HELPER(neon_qunzip16)(CPUARMState *env, uint32_t rd, uint32_t rm)
|
||||
{
|
||||
uint64_t zm0 = float64_val(env->vfp.regs[rm]);
|
||||
uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]);
|
||||
|
|
@ -1880,7 +1880,7 @@ void HELPER(neon_qunzip16)(CPUState *env, uint32_t rd, uint32_t rm)
|
|||
env->vfp.regs[rd + 1] = make_float64(d1);
|
||||
}
|
||||
|
||||
void HELPER(neon_qunzip32)(CPUState *env, uint32_t rd, uint32_t rm)
|
||||
void HELPER(neon_qunzip32)(CPUARMState *env, uint32_t rd, uint32_t rm)
|
||||
{
|
||||
uint64_t zm0 = float64_val(env->vfp.regs[rm]);
|
||||
uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]);
|
||||
|
|
@ -1896,7 +1896,7 @@ void HELPER(neon_qunzip32)(CPUState *env, uint32_t rd, uint32_t rm)
|
|||
env->vfp.regs[rd + 1] = make_float64(d1);
|
||||
}
|
||||
|
||||
void HELPER(neon_unzip8)(CPUState *env, uint32_t rd, uint32_t rm)
|
||||
void HELPER(neon_unzip8)(CPUARMState *env, uint32_t rd, uint32_t rm)
|
||||
{
|
||||
uint64_t zm = float64_val(env->vfp.regs[rm]);
|
||||
uint64_t zd = float64_val(env->vfp.regs[rd]);
|
||||
|
|
@ -1912,7 +1912,7 @@ void HELPER(neon_unzip8)(CPUState *env, uint32_t rd, uint32_t rm)
|
|||
env->vfp.regs[rd] = make_float64(d0);
|
||||
}
|
||||
|
||||
void HELPER(neon_unzip16)(CPUState *env, uint32_t rd, uint32_t rm)
|
||||
void HELPER(neon_unzip16)(CPUARMState *env, uint32_t rd, uint32_t rm)
|
||||
{
|
||||
uint64_t zm = float64_val(env->vfp.regs[rm]);
|
||||
uint64_t zd = float64_val(env->vfp.regs[rd]);
|
||||
|
|
@ -1924,7 +1924,7 @@ void HELPER(neon_unzip16)(CPUState *env, uint32_t rd, uint32_t rm)
|
|||
env->vfp.regs[rd] = make_float64(d0);
|
||||
}
|
||||
|
||||
void HELPER(neon_qzip8)(CPUState *env, uint32_t rd, uint32_t rm)
|
||||
void HELPER(neon_qzip8)(CPUARMState *env, uint32_t rd, uint32_t rm)
|
||||
{
|
||||
uint64_t zm0 = float64_val(env->vfp.regs[rm]);
|
||||
uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]);
|
||||
|
|
@ -1952,7 +1952,7 @@ void HELPER(neon_qzip8)(CPUState *env, uint32_t rd, uint32_t rm)
|
|||
env->vfp.regs[rd + 1] = make_float64(d1);
|
||||
}
|
||||
|
||||
void HELPER(neon_qzip16)(CPUState *env, uint32_t rd, uint32_t rm)
|
||||
void HELPER(neon_qzip16)(CPUARMState *env, uint32_t rd, uint32_t rm)
|
||||
{
|
||||
uint64_t zm0 = float64_val(env->vfp.regs[rm]);
|
||||
uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]);
|
||||
|
|
@ -1972,7 +1972,7 @@ void HELPER(neon_qzip16)(CPUState *env, uint32_t rd, uint32_t rm)
|
|||
env->vfp.regs[rd + 1] = make_float64(d1);
|
||||
}
|
||||
|
||||
void HELPER(neon_qzip32)(CPUState *env, uint32_t rd, uint32_t rm)
|
||||
void HELPER(neon_qzip32)(CPUARMState *env, uint32_t rd, uint32_t rm)
|
||||
{
|
||||
uint64_t zm0 = float64_val(env->vfp.regs[rm]);
|
||||
uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]);
|
||||
|
|
@ -1988,7 +1988,7 @@ void HELPER(neon_qzip32)(CPUState *env, uint32_t rd, uint32_t rm)
|
|||
env->vfp.regs[rd + 1] = make_float64(d1);
|
||||
}
|
||||
|
||||
void HELPER(neon_zip8)(CPUState *env, uint32_t rd, uint32_t rm)
|
||||
void HELPER(neon_zip8)(CPUARMState *env, uint32_t rd, uint32_t rm)
|
||||
{
|
||||
uint64_t zm = float64_val(env->vfp.regs[rm]);
|
||||
uint64_t zd = float64_val(env->vfp.regs[rd]);
|
||||
|
|
@ -2004,7 +2004,7 @@ void HELPER(neon_zip8)(CPUState *env, uint32_t rd, uint32_t rm)
|
|||
env->vfp.regs[rd] = make_float64(d0);
|
||||
}
|
||||
|
||||
void HELPER(neon_zip16)(CPUState *env, uint32_t rd, uint32_t rm)
|
||||
void HELPER(neon_zip16)(CPUARMState *env, uint32_t rd, uint32_t rm)
|
||||
{
|
||||
uint64_t zm = float64_val(env->vfp.regs[rm]);
|
||||
uint64_t zd = float64_val(env->vfp.regs[rd]);
|
||||
|
|
|
|||
|
|
@ -75,11 +75,11 @@ uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def,
|
|||
NULL, it means that the function was called in C code (i.e. not
|
||||
from generated code or from helper.c) */
|
||||
/* XXX: fix it to restore all registers */
|
||||
void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
|
||||
void tlb_fill(CPUARMState *env1, target_ulong addr, int is_write, int mmu_idx,
|
||||
void *retaddr)
|
||||
{
|
||||
TranslationBlock *tb;
|
||||
CPUState *saved_env;
|
||||
CPUARMState *saved_env;
|
||||
unsigned long pc;
|
||||
int ret;
|
||||
|
||||
|
|
@ -103,7 +103,7 @@ void tlb_fill(CPUState *env1, target_ulong addr, int is_write, int mmu_idx,
|
|||
}
|
||||
#endif
|
||||
|
||||
/* FIXME: Pass an axplicit pointer to QF to CPUState, and move saturating
|
||||
/* FIXME: Pass an axplicit pointer to QF to CPUARMState, and move saturating
|
||||
instructions into helper.c */
|
||||
uint32_t HELPER(add_setq)(uint32_t a, uint32_t b)
|
||||
{
|
||||
|
|
|
|||
|
|
@ -111,20 +111,20 @@ void arm_translate_init(void)
|
|||
|
||||
for (i = 0; i < 16; i++) {
|
||||
cpu_R[i] = tcg_global_mem_new_i32(TCG_AREG0,
|
||||
offsetof(CPUState, regs[i]),
|
||||
offsetof(CPUARMState, regs[i]),
|
||||
regnames[i]);
|
||||
}
|
||||
cpu_exclusive_addr = tcg_global_mem_new_i32(TCG_AREG0,
|
||||
offsetof(CPUState, exclusive_addr), "exclusive_addr");
|
||||
offsetof(CPUARMState, exclusive_addr), "exclusive_addr");
|
||||
cpu_exclusive_val = tcg_global_mem_new_i32(TCG_AREG0,
|
||||
offsetof(CPUState, exclusive_val), "exclusive_val");
|
||||
offsetof(CPUARMState, exclusive_val), "exclusive_val");
|
||||
cpu_exclusive_high = tcg_global_mem_new_i32(TCG_AREG0,
|
||||
offsetof(CPUState, exclusive_high), "exclusive_high");
|
||||
offsetof(CPUARMState, exclusive_high), "exclusive_high");
|
||||
#ifdef CONFIG_USER_ONLY
|
||||
cpu_exclusive_test = tcg_global_mem_new_i32(TCG_AREG0,
|
||||
offsetof(CPUState, exclusive_test), "exclusive_test");
|
||||
offsetof(CPUARMState, exclusive_test), "exclusive_test");
|
||||
cpu_exclusive_info = tcg_global_mem_new_i32(TCG_AREG0,
|
||||
offsetof(CPUState, exclusive_info), "exclusive_info");
|
||||
offsetof(CPUARMState, exclusive_info), "exclusive_info");
|
||||
#endif
|
||||
|
||||
#define GEN_HELPER 2
|
||||
|
|
@ -138,7 +138,7 @@ static inline TCGv load_cpu_offset(int offset)
|
|||
return tmp;
|
||||
}
|
||||
|
||||
#define load_cpu_field(name) load_cpu_offset(offsetof(CPUState, name))
|
||||
#define load_cpu_field(name) load_cpu_offset(offsetof(CPUARMState, name))
|
||||
|
||||
static inline void store_cpu_offset(TCGv var, int offset)
|
||||
{
|
||||
|
|
@ -147,7 +147,7 @@ static inline void store_cpu_offset(TCGv var, int offset)
|
|||
}
|
||||
|
||||
#define store_cpu_field(var, name) \
|
||||
store_cpu_offset(var, offsetof(CPUState, name))
|
||||
store_cpu_offset(var, offsetof(CPUARMState, name))
|
||||
|
||||
/* Set a variable to the value of a CPU register. */
|
||||
static void load_reg_var(DisasContext *s, TCGv var, int reg)
|
||||
|
|
@ -368,7 +368,7 @@ static void gen_add16(TCGv t0, TCGv t1)
|
|||
tcg_temp_free_i32(t1);
|
||||
}
|
||||
|
||||
#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, CF))
|
||||
#define gen_set_CF(var) tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, CF))
|
||||
|
||||
/* Set CF to the top bit of var. */
|
||||
static void gen_set_CF_bit31(TCGv var)
|
||||
|
|
@ -382,8 +382,8 @@ static void gen_set_CF_bit31(TCGv var)
|
|||
/* Set N and Z flags from var. */
|
||||
static inline void gen_logic_CC(TCGv var)
|
||||
{
|
||||
tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, NF));
|
||||
tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, ZF));
|
||||
tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, NF));
|
||||
tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, ZF));
|
||||
}
|
||||
|
||||
/* T0 += T1 + CF. */
|
||||
|
|
@ -523,13 +523,13 @@ static void gen_arm_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
|
|||
#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
|
||||
case 1:
|
||||
tmp = tcg_temp_new_ptr();
|
||||
tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
|
||||
tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
|
||||
PAS_OP(s)
|
||||
tcg_temp_free_ptr(tmp);
|
||||
break;
|
||||
case 5:
|
||||
tmp = tcg_temp_new_ptr();
|
||||
tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
|
||||
tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
|
||||
PAS_OP(u)
|
||||
tcg_temp_free_ptr(tmp);
|
||||
break;
|
||||
|
|
@ -570,13 +570,13 @@ static void gen_thumb2_parallel_addsub(int op1, int op2, TCGv a, TCGv b)
|
|||
#define gen_pas_helper(name) glue(gen_helper_,name)(a, a, b, tmp)
|
||||
case 0:
|
||||
tmp = tcg_temp_new_ptr();
|
||||
tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
|
||||
tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
|
||||
PAS_OP(s)
|
||||
tcg_temp_free_ptr(tmp);
|
||||
break;
|
||||
case 4:
|
||||
tmp = tcg_temp_new_ptr();
|
||||
tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUState, GE));
|
||||
tcg_gen_addi_ptr(tmp, cpu_env, offsetof(CPUARMState, GE));
|
||||
PAS_OP(u)
|
||||
tcg_temp_free_ptr(tmp);
|
||||
break;
|
||||
|
|
@ -725,7 +725,7 @@ static inline void gen_bx_im(DisasContext *s, uint32_t addr)
|
|||
if (s->thumb != (addr & 1)) {
|
||||
tmp = tcg_temp_new_i32();
|
||||
tcg_gen_movi_i32(tmp, addr & 1);
|
||||
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUState, thumb));
|
||||
tcg_gen_st_i32(tmp, cpu_env, offsetof(CPUARMState, thumb));
|
||||
tcg_temp_free_i32(tmp);
|
||||
}
|
||||
tcg_gen_movi_i32(cpu_R[15], addr & ~1);
|
||||
|
|
@ -743,7 +743,7 @@ static inline void gen_bx(DisasContext *s, TCGv var)
|
|||
/* Variant of store_reg which uses branch&exchange logic when storing
|
||||
to r15 in ARM architecture v7 and above. The source must be a temporary
|
||||
and will be marked as dead. */
|
||||
static inline void store_reg_bx(CPUState *env, DisasContext *s,
|
||||
static inline void store_reg_bx(CPUARMState *env, DisasContext *s,
|
||||
int reg, TCGv var)
|
||||
{
|
||||
if (reg == 15 && ENABLE_ARCH_7) {
|
||||
|
|
@ -757,7 +757,7 @@ static inline void store_reg_bx(CPUState *env, DisasContext *s,
|
|||
* to r15 in ARM architecture v5T and above. This is used for storing
|
||||
* the results of a LDR/LDM/POP into r15, and corresponds to the cases
|
||||
* in the ARM ARM which use the LoadWritePC() pseudocode function. */
|
||||
static inline void store_reg_from_load(CPUState *env, DisasContext *s,
|
||||
static inline void store_reg_from_load(CPUARMState *env, DisasContext *s,
|
||||
int reg, TCGv var)
|
||||
{
|
||||
if (reg == 15 && ENABLE_ARCH_5) {
|
||||
|
|
@ -897,9 +897,9 @@ static TCGv_ptr get_fpstatus_ptr(int neon)
|
|||
TCGv_ptr statusptr = tcg_temp_new_ptr();
|
||||
int offset;
|
||||
if (neon) {
|
||||
offset = offsetof(CPUState, vfp.standard_fp_status);
|
||||
offset = offsetof(CPUARMState, vfp.standard_fp_status);
|
||||
} else {
|
||||
offset = offsetof(CPUState, vfp.fp_status);
|
||||
offset = offsetof(CPUARMState, vfp.fp_status);
|
||||
}
|
||||
tcg_gen_addi_ptr(statusptr, cpu_env, offset);
|
||||
return statusptr;
|
||||
|
|
@ -1147,24 +1147,24 @@ static inline void gen_mov_vreg_F0(int dp, int reg)
|
|||
|
||||
static inline void iwmmxt_load_reg(TCGv_i64 var, int reg)
|
||||
{
|
||||
tcg_gen_ld_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
|
||||
tcg_gen_ld_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg]));
|
||||
}
|
||||
|
||||
static inline void iwmmxt_store_reg(TCGv_i64 var, int reg)
|
||||
{
|
||||
tcg_gen_st_i64(var, cpu_env, offsetof(CPUState, iwmmxt.regs[reg]));
|
||||
tcg_gen_st_i64(var, cpu_env, offsetof(CPUARMState, iwmmxt.regs[reg]));
|
||||
}
|
||||
|
||||
static inline TCGv iwmmxt_load_creg(int reg)
|
||||
{
|
||||
TCGv var = tcg_temp_new_i32();
|
||||
tcg_gen_ld_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
|
||||
tcg_gen_ld_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg]));
|
||||
return var;
|
||||
}
|
||||
|
||||
static inline void iwmmxt_store_creg(int reg, TCGv var)
|
||||
{
|
||||
tcg_gen_st_i32(var, cpu_env, offsetof(CPUState, iwmmxt.cregs[reg]));
|
||||
tcg_gen_st_i32(var, cpu_env, offsetof(CPUARMState, iwmmxt.cregs[reg]));
|
||||
tcg_temp_free_i32(var);
|
||||
}
|
||||
|
||||
|
|
@ -1366,7 +1366,7 @@ static inline int gen_iwmmxt_shift(uint32_t insn, uint32_t mask, TCGv dest)
|
|||
|
||||
/* Disassemble an iwMMXt instruction. Returns nonzero if an error occurred
|
||||
(ie. an undefined instruction). */
|
||||
static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
|
||||
static int disas_iwmmxt_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
|
||||
{
|
||||
int rd, wrd;
|
||||
int rdhi, rdlo, rd0, rd1, i;
|
||||
|
|
@ -2370,7 +2370,7 @@ static int disas_iwmmxt_insn(CPUState *env, DisasContext *s, uint32_t insn)
|
|||
|
||||
/* Disassemble an XScale DSP instruction. Returns nonzero if an error occurred
|
||||
(ie. an undefined instruction). */
|
||||
static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
|
||||
static int disas_dsp_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
|
||||
{
|
||||
int acc, rd0, rd1, rdhi, rdlo;
|
||||
TCGv tmp, tmp2;
|
||||
|
|
@ -2440,7 +2440,7 @@ static int disas_dsp_insn(CPUState *env, DisasContext *s, uint32_t insn)
|
|||
|
||||
/* Disassemble system coprocessor instruction. Return nonzero if
|
||||
instruction is not defined. */
|
||||
static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
|
||||
static int disas_cp_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
|
||||
{
|
||||
TCGv tmp, tmp2;
|
||||
uint32_t rd = (insn >> 12) & 0xf;
|
||||
|
|
@ -2471,7 +2471,7 @@ static int disas_cp_insn(CPUState *env, DisasContext *s, uint32_t insn)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int cp15_user_ok(CPUState *env, uint32_t insn)
|
||||
static int cp15_user_ok(CPUARMState *env, uint32_t insn)
|
||||
{
|
||||
int cpn = (insn >> 16) & 0xf;
|
||||
int cpm = insn & 0xf;
|
||||
|
|
@ -2501,7 +2501,7 @@ static int cp15_user_ok(CPUState *env, uint32_t insn)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, uint32_t rd)
|
||||
static int cp15_tls_load_store(CPUARMState *env, DisasContext *s, uint32_t insn, uint32_t rd)
|
||||
{
|
||||
TCGv tmp;
|
||||
int cpn = (insn >> 16) & 0xf;
|
||||
|
|
@ -2552,7 +2552,7 @@ static int cp15_tls_load_store(CPUState *env, DisasContext *s, uint32_t insn, ui
|
|||
|
||||
/* Disassemble system coprocessor (cp15) instruction. Return nonzero if
|
||||
instruction is not defined. */
|
||||
static int disas_cp15_insn(CPUState *env, DisasContext *s, uint32_t insn)
|
||||
static int disas_cp15_insn(CPUARMState *env, DisasContext *s, uint32_t insn)
|
||||
{
|
||||
uint32_t rd;
|
||||
TCGv tmp, tmp2;
|
||||
|
|
@ -2747,7 +2747,7 @@ static TCGv gen_load_and_replicate(DisasContext *s, TCGv addr, int size)
|
|||
|
||||
/* Disassemble a VFP instruction. Returns nonzero if an error occurred
|
||||
(ie. an undefined instruction). */
|
||||
static int disas_vfp_insn(CPUState * env, DisasContext *s, uint32_t insn)
|
||||
static int disas_vfp_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
|
||||
{
|
||||
uint32_t rd, rn, rm, op, i, n, offset, delta_d, delta_m, bank_mask;
|
||||
int dp, veclen;
|
||||
|
|
@ -3586,7 +3586,7 @@ static inline void gen_mulxy(TCGv t0, TCGv t1, int x, int y)
|
|||
}
|
||||
|
||||
/* Return the mask of PSR bits set by a MSR instruction. */
|
||||
static uint32_t msr_mask(CPUState *env, DisasContext *s, int flags, int spsr) {
|
||||
static uint32_t msr_mask(CPUARMState *env, DisasContext *s, int flags, int spsr) {
|
||||
uint32_t mask;
|
||||
|
||||
mask = 0;
|
||||
|
|
@ -3946,7 +3946,7 @@ static struct {
|
|||
|
||||
/* Translate a NEON load/store element instruction. Return nonzero if the
|
||||
instruction is invalid. */
|
||||
static int disas_neon_ls_insn(CPUState * env, DisasContext *s, uint32_t insn)
|
||||
static int disas_neon_ls_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
|
||||
{
|
||||
int rd, rn, rm;
|
||||
int op;
|
||||
|
|
@ -4622,7 +4622,7 @@ static const uint8_t neon_2rm_sizes[] = {
|
|||
We process data in a mixture of 32-bit and 64-bit chunks.
|
||||
Mostly we use 32-bit chunks so we can use normal scalar instructions. */
|
||||
|
||||
static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
|
||||
static int disas_neon_data_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
|
||||
{
|
||||
int op;
|
||||
int q;
|
||||
|
|
@ -6387,7 +6387,7 @@ static int disas_neon_data_insn(CPUState * env, DisasContext *s, uint32_t insn)
|
|||
return 0;
|
||||
}
|
||||
|
||||
static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
|
||||
static int disas_cp14_read(CPUARMState * env, DisasContext *s, uint32_t insn)
|
||||
{
|
||||
int crn = (insn >> 16) & 0xf;
|
||||
int crm = insn & 0xf;
|
||||
|
|
@ -6445,7 +6445,7 @@ static int disas_cp14_read(CPUState * env, DisasContext *s, uint32_t insn)
|
|||
return 1;
|
||||
}
|
||||
|
||||
static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
|
||||
static int disas_cp14_write(CPUARMState * env, DisasContext *s, uint32_t insn)
|
||||
{
|
||||
int crn = (insn >> 16) & 0xf;
|
||||
int crm = insn & 0xf;
|
||||
|
|
@ -6476,7 +6476,7 @@ static int disas_cp14_write(CPUState * env, DisasContext *s, uint32_t insn)
|
|||
return 1;
|
||||
}
|
||||
|
||||
static int disas_coproc_insn(CPUState * env, DisasContext *s, uint32_t insn)
|
||||
static int disas_coproc_insn(CPUARMState * env, DisasContext *s, uint32_t insn)
|
||||
{
|
||||
int cpnum;
|
||||
|
||||
|
|
@ -6696,7 +6696,7 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
|
|||
}
|
||||
#endif
|
||||
|
||||
static void disas_arm_insn(CPUState * env, DisasContext *s)
|
||||
static void disas_arm_insn(CPUARMState * env, DisasContext *s)
|
||||
{
|
||||
unsigned int cond, insn, val, op1, i, shift, rm, rs, rn, rd, sh;
|
||||
TCGv tmp;
|
||||
|
|
@ -7587,7 +7587,7 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
|
|||
tmp = load_reg(s, rn);
|
||||
tmp2 = load_reg(s, rm);
|
||||
tmp3 = tcg_temp_new_i32();
|
||||
tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
|
||||
tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE));
|
||||
gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
|
||||
tcg_temp_free_i32(tmp3);
|
||||
tcg_temp_free_i32(tmp2);
|
||||
|
|
@ -8077,7 +8077,7 @@ gen_thumb2_data_op(DisasContext *s, int op, int conds, uint32_t shifter_out, TCG
|
|||
|
||||
/* Translate a 32-bit thumb instruction. Returns nonzero if the instruction
|
||||
is not legal. */
|
||||
static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
|
||||
static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw1)
|
||||
{
|
||||
uint32_t insn, imm, shift, offset;
|
||||
uint32_t rd, rn, rm, rs;
|
||||
|
|
@ -8488,7 +8488,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
|
|||
case 0x10: /* sel */
|
||||
tmp2 = load_reg(s, rm);
|
||||
tmp3 = tcg_temp_new_i32();
|
||||
tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUState, GE));
|
||||
tcg_gen_ld_i32(tmp3, cpu_env, offsetof(CPUARMState, GE));
|
||||
gen_helper_sel_flags(tmp, tmp3, tmp, tmp2);
|
||||
tcg_temp_free_i32(tmp3);
|
||||
tcg_temp_free_i32(tmp2);
|
||||
|
|
@ -9145,7 +9145,7 @@ illegal_op:
|
|||
return 1;
|
||||
}
|
||||
|
||||
static void disas_thumb_insn(CPUState *env, DisasContext *s)
|
||||
static void disas_thumb_insn(CPUARMState *env, DisasContext *s)
|
||||
{
|
||||
uint32_t val, insn, op, rm, rn, rd, shift, cond;
|
||||
int32_t offset;
|
||||
|
|
@ -9830,7 +9830,7 @@ undef:
|
|||
/* generate intermediate code in gen_opc_buf and gen_opparam_buf for
|
||||
basic block 'tb'. If search_pc is TRUE, also generate PC
|
||||
information for each intermediate instruction. */
|
||||
static inline void gen_intermediate_code_internal(CPUState *env,
|
||||
static inline void gen_intermediate_code_internal(CPUARMState *env,
|
||||
TranslationBlock *tb,
|
||||
int search_pc)
|
||||
{
|
||||
|
|
@ -9885,22 +9885,22 @@ static inline void gen_intermediate_code_internal(CPUState *env,
|
|||
/* A note on handling of the condexec (IT) bits:
|
||||
*
|
||||
* We want to avoid the overhead of having to write the updated condexec
|
||||
* bits back to the CPUState for every instruction in an IT block. So:
|
||||
* bits back to the CPUARMState for every instruction in an IT block. So:
|
||||
* (1) if the condexec bits are not already zero then we write
|
||||
* zero back into the CPUState now. This avoids complications trying
|
||||
* zero back into the CPUARMState now. This avoids complications trying
|
||||
* to do it at the end of the block. (For example if we don't do this
|
||||
* it's hard to identify whether we can safely skip writing condexec
|
||||
* at the end of the TB, which we definitely want to do for the case
|
||||
* where a TB doesn't do anything with the IT state at all.)
|
||||
* (2) if we are going to leave the TB then we call gen_set_condexec()
|
||||
* which will write the correct value into CPUState if zero is wrong.
|
||||
* which will write the correct value into CPUARMState if zero is wrong.
|
||||
* This is done both for leaving the TB at the end, and for leaving
|
||||
* it because of an exception we know will happen, which is done in
|
||||
* gen_exception_insn(). The latter is necessary because we need to
|
||||
* leave the TB with the PC/IT state just prior to execution of the
|
||||
* instruction which caused the exception.
|
||||
* (3) if we leave the TB unexpectedly (eg a data abort on a load)
|
||||
* then the CPUState will be wrong and we need to reset it.
|
||||
* then the CPUARMState will be wrong and we need to reset it.
|
||||
* This is handled in the same way as restoration of the
|
||||
* PC in these situations: we will be called again with search_pc=1
|
||||
* and generate a mapping of the condexec bits for each PC in
|
||||
|
|
@ -9909,7 +9909,7 @@ static inline void gen_intermediate_code_internal(CPUState *env,
|
|||
*
|
||||
* Note that there are no instructions which can read the condexec
|
||||
* bits, and none which can write non-static values to them, so
|
||||
* we don't need to care about whether CPUState is correct in the
|
||||
* we don't need to care about whether CPUARMState is correct in the
|
||||
* middle of a TB.
|
||||
*/
|
||||
|
||||
|
|
@ -10103,12 +10103,12 @@ done_generating:
|
|||
}
|
||||
}
|
||||
|
||||
void gen_intermediate_code(CPUState *env, TranslationBlock *tb)
|
||||
void gen_intermediate_code(CPUARMState *env, TranslationBlock *tb)
|
||||
{
|
||||
gen_intermediate_code_internal(env, tb, 0);
|
||||
}
|
||||
|
||||
void gen_intermediate_code_pc(CPUState *env, TranslationBlock *tb)
|
||||
void gen_intermediate_code_pc(CPUARMState *env, TranslationBlock *tb)
|
||||
{
|
||||
gen_intermediate_code_internal(env, tb, 1);
|
||||
}
|
||||
|
|
@ -10118,7 +10118,7 @@ static const char *cpu_mode_names[16] = {
|
|||
"???", "???", "???", "und", "???", "???", "???", "sys"
|
||||
};
|
||||
|
||||
void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
|
||||
void cpu_dump_state(CPUARMState *env, FILE *f, fprintf_function cpu_fprintf,
|
||||
int flags)
|
||||
{
|
||||
int i;
|
||||
|
|
@ -10170,7 +10170,7 @@ void cpu_dump_state(CPUState *env, FILE *f, fprintf_function cpu_fprintf,
|
|||
#endif
|
||||
}
|
||||
|
||||
void restore_state_to_opc(CPUState *env, TranslationBlock *tb, int pc_pos)
|
||||
void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb, int pc_pos)
|
||||
{
|
||||
env->regs[15] = gen_opc_pc[pc_pos];
|
||||
env->condexec_bits = gen_opc_condexec_bits[pc_pos];
|
||||
|
|
|
|||
Loading…
Reference in New Issue