mirror of https://gitee.com/openkylin/qemu.git
hw/intc/arm_gicv3: GICD_TYPER.SecurityExtn is RAZ if GICD_CTLR.DS == 1
The GICv3 specification says that the GICD_TYPER.SecurityExtn bit is RAZ if GICD_CTLR.DS is 1. We were incorrectly making it RAZ if the security extension is unsupported. "Security extension unsupported" always implies GICD_CTLR.DS == 1, but the guest can also set DS on a GIC which does support the security extension. Fix the condition to correctly check the GICD_CTLR.DS bit. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Message-id: 20190524124248.28394-3-peter.maydell@linaro.org
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@ -378,8 +378,14 @@ static MemTxResult gicd_readl(GICv3State *s, hwaddr offset,
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* ITLinesNumber == (num external irqs / 32) - 1
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*/
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int itlinesnumber = ((s->num_irq - GIC_INTERNAL) / 32) - 1;
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/*
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* SecurityExtn must be RAZ if GICD_CTLR.DS == 1, and
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* "security extensions not supported" always implies DS == 1,
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* so we only need to check the DS bit.
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*/
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bool sec_extn = !(s->gicd_ctlr & GICD_CTLR_DS);
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*data = (1 << 25) | (1 << 24) | (s->security_extn << 10) |
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*data = (1 << 25) | (1 << 24) | (sec_extn << 10) |
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(0xf << 19) | itlinesnumber;
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return MEMTX_OK;
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}
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