From 0f921197f1a83e4fe6e71a9edef7e2a0afb712b7 Mon Sep 17 00:00:00 2001 From: Alexander Graf Date: Tue, 9 Feb 2010 17:37:02 +0100 Subject: [PATCH] PPC: Use Mac99_U3 type on ppc64 The "Mac99" type so far defines a "U2" based configuration. Unfortunately, there have never been any U2 based PPC64 machines. That's what the U3 was developed for. So let's split the Mac99 machine in a PPC64 and a PPC32 machine. The PPC32 machine stays "Mac99", while the PPC64 one becomes "Mac99_U3". All peripherals stay the same. Signed-off-by: Alexander Graf Signed-off-by: Michael S. Tsirkin --- hw/pci_ids.h | 1 + hw/ppc.h | 1 + hw/ppc_mac.h | 1 + hw/ppc_newworld.c | 12 ++++++-- hw/unin_pci.c | 70 +++++++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 83 insertions(+), 2 deletions(-) diff --git a/hw/pci_ids.h b/hw/pci_ids.h index 63379c234a..fe7a121562 100644 --- a/hw/pci_ids.h +++ b/hw/pci_ids.h @@ -63,6 +63,7 @@ #define PCI_VENDOR_ID_APPLE 0x106b #define PCI_DEVICE_ID_APPLE_UNI_N_AGP 0x0020 +#define PCI_DEVICE_ID_APPLE_U3_AGP 0x004b #define PCI_VENDOR_ID_SUN 0x108e #define PCI_DEVICE_ID_SUN_EBUS 0x1000 diff --git a/hw/ppc.h b/hw/ppc.h index bbf3a986b6..b9a12a1133 100644 --- a/hw/ppc.h +++ b/hw/ppc.h @@ -40,6 +40,7 @@ enum { ARCH_PREP = 0, ARCH_MAC99, ARCH_HEATHROW, + ARCH_MAC99_U3, }; #define FW_CFG_PPC_WIDTH (FW_CFG_ARCH_LOCAL + 0x00) diff --git a/hw/ppc_mac.h b/hw/ppc_mac.h index a04dffea84..89f96bbc34 100644 --- a/hw/ppc_mac.h +++ b/hw/ppc_mac.h @@ -58,6 +58,7 @@ PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic); /* UniNorth PCI */ PCIBus *pci_pmac_init(qemu_irq *pic); +PCIBus *pci_pmac_u3_init(qemu_irq *pic); /* Mac NVRAM */ typedef struct MacIONVRAMState MacIONVRAMState; diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c index a4c714ae7f..308e102b9a 100644 --- a/hw/ppc_newworld.c +++ b/hw/ppc_newworld.c @@ -114,6 +114,7 @@ static void ppc_core99_init (ram_addr_t ram_size, void *fw_cfg; void *dbdma; uint8_t *vga_bios_ptr; + int machine_arch; linux_boot = (kernel_filename != NULL); @@ -317,7 +318,14 @@ static void ppc_core99_init (ram_addr_t ram_size, } } pic = openpic_init(NULL, &pic_mem_index, smp_cpus, openpic_irqs, NULL); - pci_bus = pci_pmac_init(pic); + if (PPC_INPUT(env) == PPC_FLAGS_INPUT_970) { + /* 970 gets a U3 bus */ + pci_bus = pci_pmac_u3_init(pic); + machine_arch = ARCH_MAC99_U3; + } else { + pci_bus = pci_pmac_init(pic); + machine_arch = ARCH_MAC99; + } /* init basic PC hardware */ pci_vga_init(pci_bus, vga_bios_offset, vga_bios_size); @@ -364,7 +372,7 @@ static void ppc_core99_init (ram_addr_t ram_size, fw_cfg = fw_cfg_init(0, 0, CFG_ADDR, CFG_ADDR + 2); fw_cfg_add_i32(fw_cfg, FW_CFG_ID, 1); fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); - fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, ARCH_MAC99); + fw_cfg_add_i16(fw_cfg, FW_CFG_MACHINE_ID, machine_arch); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_ADDR, kernel_base); fw_cfg_add_i32(fw_cfg, FW_CFG_KERNEL_SIZE, kernel_size); if (kernel_cmdline) { diff --git a/hw/unin_pci.c b/hw/unin_pci.c index b9ff831ffa..a1493e9f8d 100644 --- a/hw/unin_pci.c +++ b/hw/unin_pci.c @@ -159,6 +159,27 @@ static int pci_unin_main_init_device(SysBusDevice *dev) return 0; } +static int pci_u3_agp_init_device(SysBusDevice *dev) +{ + UNINState *s; + int pci_mem_config, pci_mem_data; + + /* Uninorth U3 AGP bus */ + s = FROM_SYSBUS(UNINState, dev); + + pci_mem_config = pci_host_conf_register_mmio(&s->host_state); + s->data_handler.read = unin_data_read; + s->data_handler.write = unin_data_write; + pci_mem_data = cpu_register_io_memory_simple(&s->data_handler); + sysbus_init_mmio(dev, 0x1000, pci_mem_config); + sysbus_init_mmio(dev, 0x1000, pci_mem_data); + + register_savevm("uninorth", 0, 1, pci_unin_save, pci_unin_load, &s->host_state); + qemu_register_reset(pci_unin_reset, &s->host_state); + + return 0; +} + static int pci_unin_agp_init_device(SysBusDevice *dev) { UNINState *s; @@ -240,6 +261,31 @@ PCIBus *pci_pmac_init(qemu_irq *pic) return d->host_state.bus; } +PCIBus *pci_pmac_u3_init(qemu_irq *pic) +{ + DeviceState *dev; + SysBusDevice *s; + UNINState *d; + + /* Uninorth AGP bus */ + + dev = qdev_create(NULL, "u3-agp"); + qdev_init_nofail(dev); + s = sysbus_from_qdev(dev); + d = FROM_SYSBUS(UNINState, s); + + d->host_state.bus = pci_register_bus(&d->busdev.qdev, "pci", + pci_unin_set_irq, pci_unin_map_irq, + pic, 11 << 3, 4); + + sysbus_mmio_map(s, 0, 0xf0800000); + sysbus_mmio_map(s, 1, 0xf0c00000); + + pci_create_simple(d->host_state.bus, 11 << 3, "u3-agp"); + + return d->host_state.bus; +} + static int unin_main_pci_host_init(PCIDevice *d) { pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); @@ -266,6 +312,21 @@ static int unin_agp_pci_host_init(PCIDevice *d) return 0; } +static int u3_agp_pci_host_init(PCIDevice *d) +{ + pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); + pci_config_set_device_id(d->config, PCI_DEVICE_ID_APPLE_U3_AGP); + /* revision */ + d->config[0x08] = 0x00; + pci_config_set_class(d->config, PCI_CLASS_BRIDGE_HOST); + /* cache line size */ + d->config[0x0C] = 0x08; + /* latency timer */ + d->config[0x0D] = 0x10; + d->config[PCI_HEADER_TYPE] = PCI_HEADER_TYPE_NORMAL; + return 0; +} + static int unin_internal_pci_host_init(PCIDevice *d) { pci_config_set_vendor_id(d->config, PCI_VENDOR_ID_APPLE); @@ -285,6 +346,12 @@ static PCIDeviceInfo unin_main_pci_host_info = { .init = unin_main_pci_host_init, }; +static PCIDeviceInfo u3_agp_pci_host_info = { + .qdev.name = "u3-agp", + .qdev.size = sizeof(PCIDevice), + .init = u3_agp_pci_host_init, +}; + static PCIDeviceInfo unin_agp_pci_host_info = { .qdev.name = "uni-north-agp", .qdev.size = sizeof(PCIDevice), @@ -302,6 +369,9 @@ static void unin_register_devices(void) sysbus_register_dev("uni-north", sizeof(UNINState), pci_unin_main_init_device); pci_qdev_register(&unin_main_pci_host_info); + sysbus_register_dev("u3-agp", sizeof(UNINState), + pci_u3_agp_init_device); + pci_qdev_register(&u3_agp_pci_host_info); sysbus_register_dev("uni-north-agp", sizeof(UNINState), pci_unin_agp_init_device); pci_qdev_register(&unin_agp_pci_host_info);