mirror of https://gitee.com/openkylin/qemu.git
ahci: Add test_identify case to ahci-test.
Utilizing all of the bring-up code in pci_enable and hba_enable, this test issues a simple IDENTIFY command via the HBA and retrieves the response via the PIO receive mechanisms of the HBA. Bugs: The DPS interrupt (Descriptor Processed Status) does not currently get set. This will need to be adjusted in a future patch series when the AHCI DMA pathways are reworked to allow the feature, which may be utilized by OSX guests. Signed-off-by: John Snow <jsnow@redhat.com> Message-id: 1408643079-30675-9-git-send-email-jsnow@redhat.com Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
This commit is contained in:
John Snow
Stefan Hajnoczi
parent
dbc180e572
commit
0fa781e3d5
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@ -252,6 +252,97 @@
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#define AHCI_VERSION_1_2 (0x00010200)
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#define AHCI_VERSION_1_2 (0x00010200)
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#define AHCI_VERSION_1_3 (0x00010300)
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#define AHCI_VERSION_1_3 (0x00010300)
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/*** Structures ***/
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/**
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* Generic FIS structure.
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*/
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typedef struct FIS {
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uint8_t fis_type;
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uint8_t flags;
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char data[0];
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} __attribute__((__packed__)) FIS;
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/**
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* Register device-to-host FIS structure.
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*/
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typedef struct RegD2HFIS {
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/* DW0 */
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uint8_t fis_type;
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uint8_t flags;
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uint8_t status;
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uint8_t error;
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/* DW1 */
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uint8_t lba_low;
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uint8_t lba_mid;
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uint8_t lba_high;
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uint8_t device;
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/* DW2 */
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uint8_t lba3;
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uint8_t lba4;
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uint8_t lba5;
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uint8_t res1;
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/* DW3 */
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uint16_t count;
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uint8_t res2;
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uint8_t res3;
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/* DW4 */
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uint16_t res4;
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uint16_t res5;
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} __attribute__((__packed__)) RegD2HFIS;
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/**
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* Register host-to-device FIS structure.
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*/
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typedef struct RegH2DFIS {
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/* DW0 */
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uint8_t fis_type;
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uint8_t flags;
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uint8_t command;
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uint8_t feature_low;
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/* DW1 */
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uint8_t lba_low;
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uint8_t lba_mid;
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uint8_t lba_high;
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uint8_t device;
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/* DW2 */
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uint8_t lba3;
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uint8_t lba4;
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uint8_t lba5;
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uint8_t feature_high;
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/* DW3 */
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uint16_t count;
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uint8_t icc;
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uint8_t control;
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/* DW4 */
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uint32_t aux;
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} __attribute__((__packed__)) RegH2DFIS;
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/**
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* Command List entry structure.
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* The command list contains between 1-32 of these structures.
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*/
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typedef struct AHCICommand {
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uint8_t b1;
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uint8_t b2;
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uint16_t prdtl; /* Phys Region Desc. Table Length */
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uint32_t prdbc; /* Phys Region Desc. Byte Count */
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uint32_t ctba; /* Command Table Descriptor Base Address */
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uint32_t ctbau; /* '' Upper */
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uint32_t res[4];
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} __attribute__((__packed__)) AHCICommand;
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/**
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* Physical Region Descriptor; pointed to by the Command List Header,
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* struct ahci_command.
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*/
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typedef struct PRD {
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uint32_t dba; /* Data Base Address */
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uint32_t dbau; /* Data Base Address Upper */
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uint32_t res; /* Reserved */
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uint32_t dbc; /* Data Byte Count (0-indexed) & Interrupt Flag (bit 2^31) */
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} PRD;
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typedef struct HBACap {
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typedef struct HBACap {
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uint32_t cap;
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uint32_t cap;
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uint32_t cap2;
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uint32_t cap2;
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@ -289,6 +380,10 @@ static uint32_t ahci_fingerprint;
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#define PX_CLR(port, reg, mask) PX_WREG((port), (reg), \
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#define PX_CLR(port, reg, mask) PX_WREG((port), (reg), \
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PX_RREG((port), (reg)) & ~(mask));
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PX_RREG((port), (reg)) & ~(mask));
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/* For calculating how big the PRD table needs to be: */
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#define CMD_TBL_SIZ(n) ((0x80 + ((n) * sizeof(PRD)) + 0x7F) & ~0x7F)
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/*** Function Declarations ***/
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/*** Function Declarations ***/
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static QPCIDevice *get_ahci_device(void);
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static QPCIDevice *get_ahci_device(void);
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static QPCIDevice *start_ahci_device(QPCIDevice *dev, void **hba_base);
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static QPCIDevice *start_ahci_device(QPCIDevice *dev, void **hba_base);
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@ -304,6 +399,17 @@ static void ahci_test_pmcap(QPCIDevice *ahci, uint8_t offset);
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/*** Utilities ***/
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/*** Utilities ***/
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static void string_bswap16(uint16_t *s, size_t bytes)
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{
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g_assert_cmphex((bytes & 1), ==, 0);
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bytes /= 2;
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while (bytes--) {
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*s = bswap16(*s);
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s++;
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}
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}
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/**
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/**
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* Locate, verify, and return a handle to the AHCI device.
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* Locate, verify, and return a handle to the AHCI device.
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*/
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*/
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@ -418,6 +524,7 @@ static void ahci_pci_enable(QPCIDevice *ahci, void **hba_base)
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reg = qpci_config_readb(ahci, 0x92);
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reg = qpci_config_readb(ahci, 0x92);
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reg |= 0x3F;
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reg |= 0x3F;
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qpci_config_writeb(ahci, 0x92, reg);
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qpci_config_writeb(ahci, 0x92, reg);
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/* 0...0111111b -- bit significant, ports 0-5 enabled. */
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ASSERT_BIT_SET(qpci_config_readb(ahci, 0x92), 0x3F);
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ASSERT_BIT_SET(qpci_config_readb(ahci, 0x92), 0x3F);
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break;
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break;
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}
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}
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@ -1124,6 +1231,186 @@ static void ahci_test_port_spec(QPCIDevice *ahci, void *hba_base,
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}
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}
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}
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}
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/**
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* Utilizing an initialized AHCI HBA, issue an IDENTIFY command to the first
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* device we see, then read and check the response.
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*/
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static void ahci_test_identify(QPCIDevice *ahci, void *hba_base)
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{
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RegD2HFIS *d2h = g_malloc0(0x20);
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RegD2HFIS *pio = g_malloc0(0x20);
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RegH2DFIS fis;
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AHCICommand cmd;
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PRD prd;
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uint32_t ports, reg, clb, table, fb, data_ptr;
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uint16_t buff[256];
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unsigned i;
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int rc;
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g_assert(ahci != NULL);
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g_assert(hba_base != NULL);
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/* We need to:
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* (1) Create a Command Table Buffer and update the Command List Slot #0
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* to point to this buffer.
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* (2) Construct an FIS host-to-device command structure, and write it to
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* the top of the command table buffer.
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* (3) Create a data buffer for the IDENTIFY response to be sent to
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* (4) Create a Physical Region Descriptor that points to the data buffer,
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* and write it to the bottom (offset 0x80) of the command table.
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* (5) Now, PxCLB points to the command list, command 0 points to
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* our table, and our table contains an FIS instruction and a
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* PRD that points to our rx buffer.
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* (6) We inform the HBA via PxCI that there is a command ready in slot #0.
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*/
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/* Pick the first implemented and running port */
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ports = AHCI_RREG(AHCI_PI);
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for (i = 0; i < 32; ports >>= 1, ++i) {
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if (ports == 0) {
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i = 32;
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}
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if (!(ports & 0x01)) {
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continue;
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}
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reg = PX_RREG(i, AHCI_PX_CMD);
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if (BITSET(reg, AHCI_PX_CMD_ST)) {
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break;
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}
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}
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g_assert_cmphex(i, <, 32);
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g_test_message("Selected port %u for test", i);
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/* Clear out this port's interrupts (ignore the init register d2h fis) */
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reg = PX_RREG(i, AHCI_PX_IS);
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PX_WREG(i, AHCI_PX_IS, reg);
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g_assert_cmphex(PX_RREG(i, AHCI_PX_IS), ==, 0);
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/* Wipe the FIS-Recieve Buffer */
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fb = PX_RREG(i, AHCI_PX_FB);
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g_assert_cmphex(fb, !=, 0);
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qmemset(fb, 0x00, 0x100);
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/* Create a Command Table buffer. 0x80 is the smallest with a PRDTL of 0. */
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/* We need at least one PRD, so round up to the nearest 0x80 multiple. */
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table = guest_alloc(guest_malloc, CMD_TBL_SIZ(1));
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g_assert(table);
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ASSERT_BIT_CLEAR(table, 0x7F);
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/* Create a data buffer ... where we will dump the IDENTIFY data to. */
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data_ptr = guest_alloc(guest_malloc, 512);
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g_assert(data_ptr);
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/* Grab the Command List Buffer pointer */
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clb = PX_RREG(i, AHCI_PX_CLB);
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g_assert(clb);
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/* Copy the existing Command #0 structure from the CLB into local memory,
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* and build a new command #0. */
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memread(clb, &cmd, sizeof(cmd));
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cmd.b1 = 5; /* reg_h2d_fis is 5 double-words long */
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cmd.b2 = 0x04; /* clear PxTFD.STS.BSY when done */
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cmd.prdtl = cpu_to_le16(1); /* One PRD table entry. */
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cmd.prdbc = 0;
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cmd.ctba = cpu_to_le32(table);
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cmd.ctbau = 0;
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/* Construct our PRD, noting that DBC is 0-indexed. */
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prd.dba = cpu_to_le32(data_ptr);
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prd.dbau = 0;
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prd.res = 0;
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/* 511+1 bytes, request DPS interrupt */
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prd.dbc = cpu_to_le32(511 | 0x80000000);
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/* Construct our Command FIS, Based on http://wiki.osdev.org/AHCI */
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memset(&fis, 0x00, sizeof(fis));
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fis.fis_type = 0x27; /* Register Host-to-Device FIS */
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fis.command = 0xEC; /* IDENTIFY */
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fis.device = 0;
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fis.flags = 0x80; /* Indicate this is a command FIS */
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/* We've committed nothing yet, no interrupts should be posted yet. */
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g_assert_cmphex(PX_RREG(i, AHCI_PX_IS), ==, 0);
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/* Commit the Command FIS to the Command Table */
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memwrite(table, &fis, sizeof(fis));
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/* Commit the PRD entry to the Command Table */
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memwrite(table + 0x80, &prd, sizeof(prd));
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/* Commit Command #0, pointing to the Table, to the Command List Buffer. */
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memwrite(clb, &cmd, sizeof(cmd));
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/* Everything is in place, but we haven't given the go-ahead yet. */
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g_assert_cmphex(PX_RREG(i, AHCI_PX_IS), ==, 0);
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/* Issue Command #0 via PxCI */
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PX_WREG(i, AHCI_PX_CI, (1 << 0));
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while (BITSET(PX_RREG(i, AHCI_PX_TFD), AHCI_PX_TFD_STS_BSY)) {
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usleep(50);
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}
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/* Check for expected interrupts */
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reg = PX_RREG(i, AHCI_PX_IS);
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ASSERT_BIT_SET(reg, AHCI_PX_IS_DHRS);
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ASSERT_BIT_SET(reg, AHCI_PX_IS_PSS);
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/* BUG: we expect AHCI_PX_IS_DPS to be set. */
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ASSERT_BIT_CLEAR(reg, AHCI_PX_IS_DPS);
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/* Clear expected interrupts and assert all interrupts now cleared. */
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PX_WREG(i, AHCI_PX_IS, AHCI_PX_IS_DHRS | AHCI_PX_IS_PSS | AHCI_PX_IS_DPS);
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g_assert_cmphex(PX_RREG(i, AHCI_PX_IS), ==, 0);
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/* Check for errors. */
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reg = PX_RREG(i, AHCI_PX_SERR);
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g_assert_cmphex(reg, ==, 0);
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reg = PX_RREG(i, AHCI_PX_TFD);
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ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR);
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ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR);
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/* Investigate CMD #0, assert that we read 512 bytes */
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memread(clb, &cmd, sizeof(cmd));
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g_assert_cmphex(512, ==, le32_to_cpu(cmd.prdbc));
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/* Investigate FIS responses */
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memread(fb + 0x20, pio, 0x20);
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memread(fb + 0x40, d2h, 0x20);
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g_assert_cmphex(pio->fis_type, ==, 0x5f);
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g_assert_cmphex(d2h->fis_type, ==, 0x34);
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g_assert_cmphex(pio->flags, ==, d2h->flags);
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g_assert_cmphex(pio->status, ==, d2h->status);
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g_assert_cmphex(pio->error, ==, d2h->error);
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reg = PX_RREG(i, AHCI_PX_TFD);
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g_assert_cmphex((reg & AHCI_PX_TFD_ERR), ==, pio->error);
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g_assert_cmphex((reg & AHCI_PX_TFD_STS), ==, pio->status);
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/* The PIO Setup FIS contains a "bytes read" field, which is a
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* 16-bit value. The Physical Region Descriptor Byte Count is
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* 32-bit, but for small transfers using one PRD, it should match. */
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g_assert_cmphex(le16_to_cpu(pio->res4), ==, le32_to_cpu(cmd.prdbc));
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/* Last, but not least: Investigate the IDENTIFY response data. */
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memread(data_ptr, &buff, 512);
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/* Check serial number/version in the buffer */
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/* NB: IDENTIFY strings are packed in 16bit little endian chunks.
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* Since we copy byte-for-byte in ahci-test, on both LE and BE, we need to
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* unchunk this data. By contrast, ide-test copies 2 bytes at a time, and
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* as a consequence, only needs to unchunk the data on LE machines. */
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string_bswap16(&buff[10], 20);
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rc = memcmp(&buff[10], "testdisk ", 20);
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g_assert_cmphex(rc, ==, 0);
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string_bswap16(&buff[23], 8);
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rc = memcmp(&buff[23], "version ", 8);
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g_assert_cmphex(rc, ==, 0);
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g_free(d2h);
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g_free(pio);
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}
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/******************************************************************************/
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/******************************************************************************/
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/* Test Interfaces */
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/* Test Interfaces */
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/******************************************************************************/
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/******************************************************************************/
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@ -1193,6 +1480,22 @@ static void test_hba_enable(void)
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ahci_shutdown(ahci);
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ahci_shutdown(ahci);
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}
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}
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/**
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* Bring up the device and issue an IDENTIFY command.
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* Inspect the state of the HBA device and the data returned.
|
||||||
|
*/
|
||||||
|
static void test_identify(void)
|
||||||
|
{
|
||||||
|
QPCIDevice *ahci;
|
||||||
|
void *hba_base;
|
||||||
|
|
||||||
|
ahci = ahci_boot();
|
||||||
|
ahci_pci_enable(ahci, &hba_base);
|
||||||
|
ahci_hba_enable(ahci, hba_base);
|
||||||
|
ahci_test_identify(ahci, hba_base);
|
||||||
|
ahci_shutdown(ahci);
|
||||||
|
}
|
||||||
|
|
||||||
/******************************************************************************/
|
/******************************************************************************/
|
||||||
|
|
||||||
int main(int argc, char **argv)
|
int main(int argc, char **argv)
|
||||||
|
|
@ -1247,6 +1550,7 @@ int main(int argc, char **argv)
|
||||||
qtest_add_func("/ahci/pci_enable", test_pci_enable);
|
qtest_add_func("/ahci/pci_enable", test_pci_enable);
|
||||||
qtest_add_func("/ahci/hba_spec", test_hba_spec);
|
qtest_add_func("/ahci/hba_spec", test_hba_spec);
|
||||||
qtest_add_func("/ahci/hba_enable", test_hba_enable);
|
qtest_add_func("/ahci/hba_enable", test_hba_enable);
|
||||||
|
qtest_add_func("/ahci/identify", test_identify);
|
||||||
|
|
||||||
ret = g_test_run();
|
ret = g_test_run();
|
||||||
|
|
||||||
|
|
|
||||||
Loading…
Reference in New Issue