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Merge branch 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm 

* 'arm-devs.for-upstream' of git://git.linaro.org/people/pmaydell/qemu-arm:
  hw/pxa2xx.c: Fix handling of pxa2xx_i2c variable offset within region
  hw/pxa2xx_lcd.c: drop target_phys_addr_t usage in device state
  hw/pxa2xx_dma.c: drop target_phys_addr_t usage in device state
  ARM: Remove unnecessary subpage workarounds
  hw/omap_i2c: Convert to qdev
This commit is contained in:
Blue Swirl 2012-03-17 16:23:19 +00:00
parent 69784eaec3 14dd5faa7e
commit 103f9af2a1
11 changed files with 120 additions and 103 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
hw/arm11mpcore.c
View File

@ -42,7 +42,6 @@ static uint64_t mpcore_scu_read(void *opaque, target_phys_addr_t offset,
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
int id;
offset &= 0xff;
/* SCU */
switch (offset) {
case 0x00: /* Control. */
@ -63,7 +62,6 @@ static void mpcore_scu_write(void *opaque, target_phys_addr_t offset,
uint64_t value, unsigned size)
{
mpcore_priv_state *s = (mpcore_priv_state *)opaque;
offset &= 0xff;
/* SCU */
switch (offset) {
case 0: /* Control register. */

8
hw/arm_gic.c
View File

@ -658,14 +658,14 @@ static uint64_t gic_thiscpu_read(void *opaque, target_phys_addr_t addr,
unsigned size)
{
gic_state *s = (gic_state *)opaque;
return gic_cpu_read(s, gic_get_current_cpu(), addr & 0xff);
return gic_cpu_read(s, gic_get_current_cpu(), addr);
}
static void gic_thiscpu_write(void *opaque, target_phys_addr_t addr,
uint64_t value, unsigned size)
{
gic_state *s = (gic_state *)opaque;
gic_cpu_write(s, gic_get_current_cpu(), addr & 0xff, value);
gic_cpu_write(s, gic_get_current_cpu(), addr, value);
}
/* Wrappers to read/write the GIC CPU interface for a specific CPU.
@ -677,7 +677,7 @@ static uint64_t gic_do_cpu_read(void *opaque, target_phys_addr_t addr,
gic_state **backref = (gic_state **)opaque;
gic_state *s = *backref;
int id = (backref - s->backref);
return gic_cpu_read(s, id, addr & 0xff);
return gic_cpu_read(s, id, addr);
}
static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr,
@ -686,7 +686,7 @@ static void gic_do_cpu_write(void *opaque, target_phys_addr_t addr,
gic_state **backref = (gic_state **)opaque;
gic_state *s = *backref;
int id = (backref - s->backref);
gic_cpu_write(s, id, addr & 0xff, value);
gic_cpu_write(s, id, addr, value);
}
static const MemoryRegionOps gic_thiscpu_ops = {

2
hw/arm_mptimer.c
View File

@ -97,7 +97,6 @@ static uint64_t timerblock_read(void *opaque, target_phys_addr_t addr,
{
timerblock *tb = (timerblock *)opaque;
int64_t val;
addr &= 0x1f;
switch (addr) {
case 0: /* Load */
return tb->load;
@ -126,7 +125,6 @@ static void timerblock_write(void *opaque, target_phys_addr_t addr,
{
timerblock *tb = (timerblock *)opaque;
int64_t old;
addr &= 0x1f;
switch (addr) {
case 0: /* Load */
tb->load = value;

12
hw/nseries.c
View File

@ -45,7 +45,6 @@ struct n800_s {
uint32_t (*txrx)(void *opaque, uint32_t value, int len);
uWireSlave *chip;
} ts;
i2c_bus *i2c;
int keymap[0x80];
DeviceState *kbd;
@ -194,12 +193,10 @@ static void n8x0_i2c_setup(struct n800_s *s)
{
DeviceState *dev;
qemu_irq tmp_irq = qdev_get_gpio_in(s->cpu->gpio, N8X0_TMP105_GPIO);
/* Attach the CPU on one end of our I2C bus. */
s->i2c = omap_i2c_bus(s->cpu->i2c[0]);
i2c_bus *i2c = omap_i2c_bus(s->cpu->i2c[0]);
/* Attach a menelaus PM chip */
dev = i2c_create_slave(s->i2c, "twl92230", N8X0_MENELAUS_ADDR);
dev = i2c_create_slave(i2c, "twl92230", N8X0_MENELAUS_ADDR);
qdev_connect_gpio_out(dev, 3,
qdev_get_gpio_in(s->cpu->ih[0],
OMAP_INT_24XX_SYS_NIRQ));
@ -207,7 +204,7 @@ static void n8x0_i2c_setup(struct n800_s *s)
qemu_system_powerdown = qdev_get_gpio_in(dev, 3);
/* Attach a TMP105 PM chip (A0 wired to ground) */
dev = i2c_create_slave(s->i2c, "tmp105", N8X0_TMP105_ADDR);
dev = i2c_create_slave(i2c, "tmp105", N8X0_TMP105_ADDR);
qdev_connect_gpio_out(dev, 0, tmp_irq);
}
@ -391,7 +388,8 @@ static void n810_kbd_setup(struct n800_s *s)
/* Attach the LM8322 keyboard to the I2C bus,
* should happen in n8x0_i2c_setup and s->kbd be initialised here. */
s->kbd = i2c_create_slave(s->i2c, "lm8323", N810_LM8323_ADDR);
s->kbd = i2c_create_slave(omap_i2c_bus(s->cpu->i2c[0]),
"lm8323", N810_LM8323_ADDR);
qdev_connect_gpio_out(s->kbd, 0, kbd_irq);
}

13
hw/omap.h
View File

@ -764,16 +764,7 @@ void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
void omap_mmc_enable(struct omap_mmc_s *s, int enable);
/* omap_i2c.c */
struct omap_i2c_s;
struct omap_i2c_s *omap_i2c_init(MemoryRegion *sysmem,
target_phys_addr_t base,
qemu_irq irq,
qemu_irq *dma,
omap_clk clk);
struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk);
void omap_i2c_reset(struct omap_i2c_s *s);
i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
i2c_bus *omap_i2c_bus(DeviceState *omap_i2c);
# define cpu_is_omap310(cpu) (cpu->mpu_model == omap310)
# define cpu_is_omap1510(cpu) (cpu->mpu_model == omap1510)
@ -867,7 +858,7 @@ struct omap_mpu_state_s {
struct omap_pwl_s *pwl;
struct omap_pwt_s *pwt;
struct omap_i2c_s *i2c[2];
DeviceState *i2c[2];
struct omap_rtc_s *rtc;

13
hw/omap1.c
View File

@ -3694,7 +3694,6 @@ static void omap1_mpu_reset(void *opaque)
omap_uwire_reset(mpu->microwire);
omap_pwl_reset(mpu->pwl);
omap_pwt_reset(mpu->pwt);
omap_i2c_reset(mpu->i2c[0]);
omap_rtc_reset(mpu->rtc);
omap_mcbsp_reset(mpu->mcbsp1);
omap_mcbsp_reset(mpu->mcbsp2);
@ -3993,9 +3992,15 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory,
s->pwt = omap_pwt_init(system_memory, 0xfffb6000,
omap_findclk(s, "armxor_ck"));
s->i2c[0] = omap_i2c_init(system_memory, 0xfffb3800,
qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C),
&s->drq[OMAP_DMA_I2C_RX], omap_findclk(s, "mpuper_ck"));
s->i2c[0] = qdev_create(NULL, "omap_i2c");
qdev_prop_set_uint8(s->i2c[0], "revision", 0x11);
qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "mpuper_ck"));
qdev_init_nofail(s->i2c[0]);
busdev = sysbus_from_qdev(s->i2c[0]);
sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(s->ih[1], OMAP_INT_I2C));
sysbus_connect_irq(busdev, 1, s->drq[OMAP_DMA_I2C_TX]);
sysbus_connect_irq(busdev, 2, s->drq[OMAP_DMA_I2C_RX]);
sysbus_mmio_map(busdev, 0, 0xfffb3800);
s->rtc = omap_rtc_init(system_memory, 0xfffb4800,
qdev_get_gpio_in(s->ih[1], OMAP_INT_RTC_TIMER),

35
hw/omap2.c
View File

@ -2222,8 +2222,6 @@ static void omap2_mpu_reset(void *opaque)
omap_mmc_reset(mpu->mmc);
omap_mcspi_reset(mpu->mcspi[0]);
omap_mcspi_reset(mpu->mcspi[1]);
omap_i2c_reset(mpu->i2c[0]);
omap_i2c_reset(mpu->i2c[1]);
cpu_state_reset(mpu->env);
}
@ -2395,16 +2393,29 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem,
omap_findclk(s, "clk32-kHz"),
omap_findclk(s, "core_l4_iclk"));
s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5),
qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ),
&s->drq[OMAP24XX_DMA_I2C1_TX],
omap_findclk(s, "i2c1.fclk"),
omap_findclk(s, "i2c1.iclk"));
s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6),
qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ),
&s->drq[OMAP24XX_DMA_I2C2_TX],
omap_findclk(s, "i2c2.fclk"),
omap_findclk(s, "i2c2.iclk"));
s->i2c[0] = qdev_create(NULL, "omap_i2c");
qdev_prop_set_uint8(s->i2c[0], "revision", 0x34);
qdev_prop_set_ptr(s->i2c[0], "iclk", omap_findclk(s, "i2c1.iclk"));
qdev_prop_set_ptr(s->i2c[0], "fclk", omap_findclk(s, "i2c1.fclk"));
qdev_init_nofail(s->i2c[0]);
busdev = sysbus_from_qdev(s->i2c[0]);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C1_IRQ));
sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C1_TX]);
sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C1_RX]);
sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 5), 0));
s->i2c[1] = qdev_create(NULL, "omap_i2c");
qdev_prop_set_uint8(s->i2c[1], "revision", 0x34);
qdev_prop_set_ptr(s->i2c[1], "iclk", omap_findclk(s, "i2c2.iclk"));
qdev_prop_set_ptr(s->i2c[1], "fclk", omap_findclk(s, "i2c2.fclk"));
qdev_init_nofail(s->i2c[1]);
busdev = sysbus_from_qdev(s->i2c[1]);
sysbus_connect_irq(busdev, 0,
qdev_get_gpio_in(s->ih[0], OMAP_INT_24XX_I2C2_IRQ));
sysbus_connect_irq(busdev, 1, s->drq[OMAP24XX_DMA_I2C2_TX]);
sysbus_connect_irq(busdev, 2, s->drq[OMAP24XX_DMA_I2C2_RX]);
sysbus_mmio_map(busdev, 0, omap_l4_region_base(omap_l4tao(s->l4, 6), 0));
s->gpio = qdev_create(NULL, "omap2-gpio");
qdev_prop_set_int32(s->gpio, "mpu_model", s->mpu_model);

111
hw/omap_i2c.c
View File

@ -19,14 +19,20 @@
#include "hw.h"
#include "i2c.h"
#include "omap.h"
#include "sysbus.h"
struct omap_i2c_s {
typedef struct OMAPI2CState {
SysBusDevice busdev;
MemoryRegion iomem;
qemu_irq irq;
qemu_irq drq[2];
i2c_bus *bus;
uint8_t revision;
void *iclk;
void *fclk;
uint8_t mask;
uint16_t stat;
uint16_t dma;
@ -40,12 +46,12 @@ struct omap_i2c_s {
uint8_t divider;
uint8_t times[2];
uint16_t test;
};
} OMAPI2CState;
#define OMAP2_INTR_REV 0x34
#define OMAP2_GC_REV 0x34
static void omap_i2c_interrupts_update(struct omap_i2c_s *s)
static void omap_i2c_interrupts_update(OMAPI2CState *s)
{
qemu_set_irq(s->irq, s->stat & s->mask);
if ((s->dma >> 15) & 1) /* RDMA_EN */
@ -54,7 +60,7 @@ static void omap_i2c_interrupts_update(struct omap_i2c_s *s)
qemu_set_irq(s->drq[1], (s->stat >> 4) & 1); /* XRDY */
}
static void omap_i2c_fifo_run(struct omap_i2c_s *s)
static void omap_i2c_fifo_run(OMAPI2CState *s)
{
int ack = 1;
@ -122,8 +128,10 @@ static void omap_i2c_fifo_run(struct omap_i2c_s *s)
s->control &= ~(1 << 1); /* STP */
}
void omap_i2c_reset(struct omap_i2c_s *s)
static void omap_i2c_reset(DeviceState *dev)
{
OMAPI2CState *s = FROM_SYSBUS(OMAPI2CState,
sysbus_from_qdev(dev));
s->mask = 0;
s->stat = 0;
s->dma = 0;
@ -143,7 +151,7 @@ void omap_i2c_reset(struct omap_i2c_s *s)
static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
{
struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
OMAPI2CState *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
uint16_t ret;
@ -243,7 +251,7 @@ static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
OMAPI2CState *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
int nack;
@ -309,14 +317,14 @@ static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
}
if (value & 2)
omap_i2c_reset(s);
omap_i2c_reset(&s->busdev.qdev);
break;
case 0x24: /* I2C_CON */
s->control = value & 0xcf87;
if (~value & (1 << 15)) { /* I2C_EN */
if (s->revision < OMAP2_INTR_REV)
omap_i2c_reset(s);
omap_i2c_reset(&s->busdev.qdev);
break;
}
if ((value & (1 << 15)) && !(value & (1 << 10))) { /* MST */
@ -385,7 +393,7 @@ static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr,
uint32_t value)
{
struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
OMAPI2CState *s = opaque;
int offset = addr & OMAP_MPUI_REG_MASK;
switch (offset) {
@ -426,50 +434,59 @@ static const MemoryRegionOps omap_i2c_ops = {
.endianness = DEVICE_NATIVE_ENDIAN,
};
struct omap_i2c_s *omap_i2c_init(MemoryRegion *sysmem,
target_phys_addr_t base,
qemu_irq irq,
qemu_irq *dma,
omap_clk clk)
static int omap_i2c_init(SysBusDevice *dev)
{
struct omap_i2c_s *s = (struct omap_i2c_s *)
g_malloc0(sizeof(struct omap_i2c_s));
OMAPI2CState *s = FROM_SYSBUS(OMAPI2CState, dev);
/* TODO: set a value greater or equal to real hardware */
s->revision = 0x11;
s->irq = irq;
s->drq[0] = dma[0];
s->drq[1] = dma[1];
s->bus = i2c_init_bus(NULL, "i2c");
omap_i2c_reset(s);
memory_region_init_io(&s->iomem, &omap_i2c_ops, s, "omap.i2c", 0x800);
memory_region_add_subregion(sysmem, base, &s->iomem);
return s;
if (!s->fclk) {
hw_error("omap_i2c: fclk not connected\n");
}
if (s->revision >= OMAP2_INTR_REV && !s->iclk) {
/* Note that OMAP1 doesn't have a separate interface clock */
hw_error("omap_i2c: iclk not connected\n");
}
sysbus_init_irq(dev, &s->irq);
sysbus_init_irq(dev, &s->drq[0]);
sysbus_init_irq(dev, &s->drq[1]);
memory_region_init_io(&s->iomem, &omap_i2c_ops, s, "omap.i2c",
(s->revision < OMAP2_INTR_REV) ? 0x800 : 0x1000);
sysbus_init_mmio(dev, &s->iomem);
s->bus = i2c_init_bus(&dev->qdev, NULL);
return 0;
}
struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk)
static Property omap_i2c_properties[] = {
DEFINE_PROP_UINT8("revision", OMAPI2CState, revision, 0),
DEFINE_PROP_PTR("iclk", OMAPI2CState, iclk),
DEFINE_PROP_PTR("fclk", OMAPI2CState, fclk),
DEFINE_PROP_END_OF_LIST(),
};
static void omap_i2c_class_init(ObjectClass *klass, void *data)
{
struct omap_i2c_s *s = (struct omap_i2c_s *)
g_malloc0(sizeof(struct omap_i2c_s));
s->revision = 0x34;
s->irq = irq;
s->drq[0] = dma[0];
s->drq[1] = dma[1];
s->bus = i2c_init_bus(NULL, "i2c");
omap_i2c_reset(s);
memory_region_init_io(&s->iomem, &omap_i2c_ops, s, "omap2.i2c",
omap_l4_region_size(ta, 0));
omap_l4_attach(ta, 0, &s->iomem);
return s;
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = omap_i2c_init;
dc->props = omap_i2c_properties;
dc->reset = omap_i2c_reset;
}
i2c_bus *omap_i2c_bus(struct omap_i2c_s *s)
static TypeInfo omap_i2c_info = {
.name = "omap_i2c",
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(OMAPI2CState),
.class_init = omap_i2c_class_init,
};
static void omap_i2c_register_types(void)
{
type_register_static(&omap_i2c_info);
}
i2c_bus *omap_i2c_bus(DeviceState *omap_i2c)
{
OMAPI2CState *s = FROM_SYSBUS(OMAPI2CState, sysbus_from_qdev(omap_i2c));
return s->bus;
}
type_init(omap_i2c_register_types)

3
hw/pxa2xx.c
View File

@ -1507,8 +1507,7 @@ PXA2xxI2CState *pxa2xx_i2c_init(target_phys_addr_t base,
i2c_dev = sysbus_from_qdev(qdev_create(NULL, "pxa2xx_i2c"));
qdev_prop_set_uint32(&i2c_dev->qdev, "size", region_size + 1);
qdev_prop_set_uint32(&i2c_dev->qdev, "offset",
base - (base & (~region_size) & TARGET_PAGE_MASK));
qdev_prop_set_uint32(&i2c_dev->qdev, "offset", base & region_size);
qdev_init_nofail(&i2c_dev->qdev);

12
hw/pxa2xx_dma.c
View File

@ -18,9 +18,9 @@
#define PXA2XX_DMA_NUM_REQUESTS 75
typedef struct {
target_phys_addr_t descr;
target_phys_addr_t src;
target_phys_addr_t dest;
uint32_t descr;
uint32_t src;
uint32_t dest;
uint32_t cmd;
uint32_t state;
int request;
@ -512,9 +512,9 @@ static VMStateDescription vmstate_pxa2xx_dma_chan = {
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_UINTTL(descr, PXA2xxDMAChannel),
VMSTATE_UINTTL(src, PXA2xxDMAChannel),
VMSTATE_UINTTL(dest, PXA2xxDMAChannel),
VMSTATE_UINT32(descr, PXA2xxDMAChannel),
VMSTATE_UINT32(src, PXA2xxDMAChannel),
VMSTATE_UINT32(dest, PXA2xxDMAChannel),
VMSTATE_UINT32(cmd, PXA2xxDMAChannel),
VMSTATE_UINT32(state, PXA2xxDMAChannel),
VMSTATE_INT32(request, PXA2xxDMAChannel),

12
hw/pxa2xx_lcd.c
View File

@ -19,15 +19,15 @@
#include "framebuffer.h"
struct DMAChannel {
target_phys_addr_t branch;
uint32_t branch;
uint8_t up;
uint8_t palette[1024];
uint8_t pbuffer[1024];
void (*redraw)(PXA2xxLCDState *s, target_phys_addr_t addr,
int *miny, int *maxy);
target_phys_addr_t descriptor;
target_phys_addr_t source;
uint32_t descriptor;
uint32_t source;
uint32_t id;
uint32_t command;
};
@ -929,11 +929,11 @@ static const VMStateDescription vmstate_dma_channel = {
.minimum_version_id = 0,
.minimum_version_id_old = 0,
.fields = (VMStateField[]) {
VMSTATE_UINTTL(branch, struct DMAChannel),
VMSTATE_UINT32(branch, struct DMAChannel),
VMSTATE_UINT8(up, struct DMAChannel),
VMSTATE_BUFFER(pbuffer, struct DMAChannel),
VMSTATE_UINTTL(descriptor, struct DMAChannel),
VMSTATE_UINTTL(source, struct DMAChannel),
VMSTATE_UINT32(descriptor, struct DMAChannel),
VMSTATE_UINT32(source, struct DMAChannel),
VMSTATE_UINT32(id, struct DMAChannel),
VMSTATE_UINT32(command, struct DMAChannel),
VMSTATE_END_OF_LIST()