mirror of https://gitee.com/openkylin/qemu.git
target/xtensa: add MX interrupt controller
MX interrupt controller is a collection of the following devices accessible through the external registers interface: - interrupt distributor can route each external IRQ line to the corresponding external IRQ pin of selected subset of connected xtensa cores. It has per-CPU and per-IRQ enable signals and per-IRQ software assert signals; - IPI controller has 16 per-CPU IPI signals that may be routed to a combination of 3 designated external IRQ pins of connected xtensa cores; - cache coherecy register controls core L1 cache participation in the SMP cluster cache coherency protocol; - runstall register lets BSP core stall and unstall AP cores. Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
This commit is contained in:
Max Filippov
parent
17a86b0e9f
commit
10df8ff146
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@ -1,3 +1,4 @@
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obj-y += mx_pic.o
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obj-y += pic_cpu.o
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obj-y += sim.o
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obj-y += xtensa_memory.o
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@ -0,0 +1,354 @@
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/*
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* Copyright (c) 2013 - 2019, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions are met:
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* * Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* * Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* * Neither the name of the Open Source and Linux Lab nor the
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* names of its contributors may be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
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* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
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* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
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* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
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* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#include "qemu/osdep.h"
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#include "hw/hw.h"
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#include "hw/xtensa/mx_pic.h"
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#include "qemu/log.h"
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#define MX_MAX_CPU 32
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#define MX_MAX_IRQ 32
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#define MIROUT 0x0
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#define MIPICAUSE 0x100
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#define MIPISET 0x140
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#define MIENG 0x180
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#define MIENGSET 0x184
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#define MIASG 0x188
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#define MIASGSET 0x18c
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#define MIPIPART 0x190
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#define SYSCFGID 0x1a0
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#define MPSCORE 0x200
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#define CCON 0x220
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struct XtensaMxPic {
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unsigned n_cpu;
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unsigned n_irq;
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uint32_t ext_irq_state;
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uint32_t mieng;
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uint32_t miasg;
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uint32_t mirout[MX_MAX_IRQ];
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uint32_t mipipart;
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uint32_t runstall;
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qemu_irq *irq_inputs;
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struct XtensaMxPicCpu {
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XtensaMxPic *mx;
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qemu_irq *irq;
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qemu_irq runstall;
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uint32_t mipicause;
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uint32_t mirout_cache;
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uint32_t irq_state_cache;
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uint32_t ccon;
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MemoryRegion reg;
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} cpu[MX_MAX_CPU];
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};
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static uint64_t xtensa_mx_pic_ext_reg_read(void *opaque, hwaddr offset,
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unsigned size)
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{
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struct XtensaMxPicCpu *mx_cpu = opaque;
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struct XtensaMxPic *mx = mx_cpu->mx;
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if (offset < MIROUT + MX_MAX_IRQ) {
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return mx->mirout[offset - MIROUT];
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} else if (offset >= MIPICAUSE && offset < MIPICAUSE + MX_MAX_CPU) {
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return mx->cpu[offset - MIPICAUSE].mipicause;
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} else {
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switch (offset) {
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case MIENG:
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return mx->mieng;
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case MIASG:
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return mx->miasg;
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case MIPIPART:
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return mx->mipipart;
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case SYSCFGID:
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return ((mx->n_cpu - 1) << 18) | (mx_cpu - mx->cpu);
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case MPSCORE:
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return mx->runstall;
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case CCON:
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return mx_cpu->ccon;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"unknown RER in MX PIC range: 0x%08x\n",
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(uint32_t)offset);
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return 0;
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}
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}
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}
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static uint32_t xtensa_mx_pic_get_ipi_for_cpu(const XtensaMxPic *mx,
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unsigned cpu)
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{
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uint32_t mipicause = mx->cpu[cpu].mipicause;
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uint32_t mipipart = mx->mipipart;
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return (((mipicause & 1) << (mipipart & 3)) |
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((mipicause & 0x000e) != 0) << ((mipipart >> 2) & 3) |
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((mipicause & 0x00f0) != 0) << ((mipipart >> 4) & 3) |
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((mipicause & 0xff00) != 0) << ((mipipart >> 6) & 3)) & 0x7;
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}
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static uint32_t xtensa_mx_pic_get_ext_irq_for_cpu(const XtensaMxPic *mx,
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unsigned cpu)
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{
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return ((((mx->ext_irq_state & mx->mieng) | mx->miasg) &
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mx->cpu[cpu].mirout_cache) << 2) |
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xtensa_mx_pic_get_ipi_for_cpu(mx, cpu);
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}
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static void xtensa_mx_pic_update_cpu(XtensaMxPic *mx, unsigned cpu)
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{
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uint32_t irq = xtensa_mx_pic_get_ext_irq_for_cpu(mx, cpu);
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uint32_t changed_irq = mx->cpu[cpu].irq_state_cache ^ irq;
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unsigned i;
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qemu_log_mask(CPU_LOG_INT, "%s: CPU %d, irq: %08x, changed_irq: %08x\n",
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__func__, cpu, irq, changed_irq);
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mx->cpu[cpu].irq_state_cache = irq;
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for (i = 0; changed_irq; ++i) {
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uint32_t mask = 1u << i;
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if (changed_irq & mask) {
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changed_irq ^= mask;
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qemu_set_irq(mx->cpu[cpu].irq[i], irq & mask);
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}
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}
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}
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static void xtensa_mx_pic_update_all(XtensaMxPic *mx)
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{
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unsigned cpu;
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for (cpu = 0; cpu < mx->n_cpu; ++cpu) {
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xtensa_mx_pic_update_cpu(mx, cpu);
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}
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}
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static void xtensa_mx_pic_ext_reg_write(void *opaque, hwaddr offset,
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uint64_t v, unsigned size)
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{
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struct XtensaMxPicCpu *mx_cpu = opaque;
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struct XtensaMxPic *mx = mx_cpu->mx;
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unsigned cpu;
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if (offset < MIROUT + mx->n_irq) {
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mx->mirout[offset - MIROUT] = v;
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for (cpu = 0; cpu < mx->n_cpu; ++cpu) {
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uint32_t mask = 1u << (offset - MIROUT);
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if (!(mx->cpu[cpu].mirout_cache & mask) != !(v & (1u << cpu))) {
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mx->cpu[cpu].mirout_cache ^= mask;
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xtensa_mx_pic_update_cpu(mx, cpu);
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}
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}
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} else if (offset >= MIPICAUSE && offset < MIPICAUSE + mx->n_cpu) {
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cpu = offset - MIPICAUSE;
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mx->cpu[cpu].mipicause &= ~v;
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xtensa_mx_pic_update_cpu(mx, cpu);
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} else if (offset >= MIPISET && offset < MIPISET + 16) {
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for (cpu = 0; cpu < mx->n_cpu; ++cpu) {
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if (v & (1u << cpu)) {
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mx->cpu[cpu].mipicause |= 1u << (offset - MIPISET);
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xtensa_mx_pic_update_cpu(mx, cpu);
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}
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}
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} else {
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uint32_t change = 0;
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uint32_t oldv, newv;
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const char *name = "???";
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switch (offset) {
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case MIENG:
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change = mx->mieng & v;
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oldv = mx->mieng;
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mx->mieng &= ~v;
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newv = mx->mieng;
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name = "MIENG";
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break;
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case MIENGSET:
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change = ~mx->mieng & v;
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oldv = mx->mieng;
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mx->mieng |= v;
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newv = mx->mieng;
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name = "MIENG";
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break;
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case MIASG:
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change = mx->miasg & v;
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oldv = mx->miasg;
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mx->miasg &= ~v;
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newv = mx->miasg;
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name = "MIASG";
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break;
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case MIASGSET:
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change = ~mx->miasg & v;
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oldv = mx->miasg;
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mx->miasg |= v;
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newv = mx->miasg;
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name = "MIASG";
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break;
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case MIPIPART:
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change = mx->mipipart ^ v;
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oldv = mx->mipipart;
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mx->mipipart = v;
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newv = mx->mipipart;
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name = "MIPIPART";
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break;
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case MPSCORE:
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change = mx->runstall ^ v;
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oldv = mx->runstall;
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mx->runstall = v;
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newv = mx->runstall;
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name = "RUNSTALL";
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for (cpu = 0; cpu < mx->n_cpu; ++cpu) {
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if (change & (1u << cpu)) {
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qemu_set_irq(mx->cpu[cpu].runstall, v & (1u << cpu));
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}
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}
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break;
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case CCON:
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mx_cpu->ccon = v & 0x1;
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break;
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default:
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qemu_log_mask(LOG_GUEST_ERROR,
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"unknown WER in MX PIC range: 0x%08x = 0x%08x\n",
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(uint32_t)offset, (uint32_t)v);
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break;
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}
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if (change) {
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qemu_log_mask(CPU_LOG_INT,
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"%s: %s changed by CPU %d: %08x -> %08x\n",
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__func__, name, (int)(mx_cpu - mx->cpu),
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oldv, newv);
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xtensa_mx_pic_update_all(mx);
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}
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}
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}
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static const MemoryRegionOps xtensa_mx_pic_ops = {
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.read = xtensa_mx_pic_ext_reg_read,
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.write = xtensa_mx_pic_ext_reg_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.unaligned = true,
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},
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};
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MemoryRegion *xtensa_mx_pic_register_cpu(XtensaMxPic *mx,
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qemu_irq *irq,
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qemu_irq runstall)
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{
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struct XtensaMxPicCpu *mx_cpu = mx->cpu + mx->n_cpu;
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mx_cpu->mx = mx;
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mx_cpu->irq = irq;
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mx_cpu->runstall = runstall;
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memory_region_init_io(&mx_cpu->reg, NULL, &xtensa_mx_pic_ops, mx_cpu,
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"mx_pic", 0x280);
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++mx->n_cpu;
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return &mx_cpu->reg;
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}
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static void xtensa_mx_pic_set_irq(void *opaque, int irq, int active)
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{
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XtensaMxPic *mx = opaque;
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if (irq < mx->n_irq) {
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uint32_t old_irq_state = mx->ext_irq_state;
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if (active) {
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mx->ext_irq_state |= 1u << irq;
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} else {
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mx->ext_irq_state &= ~(1u << irq);
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}
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if (old_irq_state != mx->ext_irq_state) {
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qemu_log_mask(CPU_LOG_INT,
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"%s: IRQ %d, active: %d, ext_irq_state: %08x -> %08x\n",
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__func__, irq, active,
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old_irq_state, mx->ext_irq_state);
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xtensa_mx_pic_update_all(mx);
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}
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} else {
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qemu_log_mask(LOG_GUEST_ERROR, "%s: IRQ %d out of range\n",
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__func__, irq);
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}
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}
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XtensaMxPic *xtensa_mx_pic_init(unsigned n_irq)
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{
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XtensaMxPic *mx = calloc(1, sizeof(XtensaMxPic));
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mx->n_irq = n_irq + 1;
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mx->irq_inputs = qemu_allocate_irqs(xtensa_mx_pic_set_irq, mx,
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mx->n_irq);
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return mx;
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}
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void xtensa_mx_pic_reset(void *opaque)
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{
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XtensaMxPic *mx = opaque;
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unsigned i;
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mx->ext_irq_state = 0;
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mx->mieng = mx->n_irq < 32 ? (1u << mx->n_irq) - 1 : ~0u;
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mx->miasg = 0;
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mx->mipipart = 0;
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for (i = 0; i < mx->n_irq; ++i) {
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mx->mirout[i] = 1;
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}
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for (i = 0; i < mx->n_cpu; ++i) {
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mx->cpu[i].mipicause = 0;
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mx->cpu[i].mirout_cache = i ? 0 : mx->mieng;
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mx->cpu[i].irq_state_cache = 0;
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mx->cpu[i].ccon = 0;
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}
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mx->runstall = (1u << mx->n_cpu) - 2;
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for (i = 0; i < mx->n_cpu; ++i) {
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qemu_set_irq(mx->cpu[i].runstall, i > 0);
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}
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}
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qemu_irq *xtensa_mx_pic_get_extints(XtensaMxPic *mx)
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{
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return mx->irq_inputs + 1;
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}
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@ -0,0 +1,44 @@
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/*
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* Copyright (c) 2013 - 2019, Max Filippov, Open Source and Linux Lab.
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* All rights reserved.
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*
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* Redistribution and use in source and binary forms, with or without
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||||
* modification, are permitted provided that the following conditions are met:
|
||||
* * Redistributions of source code must retain the above copyright
|
||||
* notice, this list of conditions and the following disclaimer.
|
||||
* * Redistributions in binary form must reproduce the above copyright
|
||||
* notice, this list of conditions and the following disclaimer in the
|
||||
* documentation and/or other materials provided with the distribution.
|
||||
* * Neither the name of the Open Source and Linux Lab nor the
|
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* names of its contributors may be used to endorse or promote products
|
||||
* derived from this software without specific prior written permission.
|
||||
*
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||||
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
* ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
|
||||
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
|
||||
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
|
||||
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
|
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* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*/
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#ifndef _XTENSA_MX_PIC_H
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#define _XTENSA_MX_PIC_H
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#include "exec/memory.h"
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#include "hw/irq.h"
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struct XtensaMxPic;
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typedef struct XtensaMxPic XtensaMxPic;
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XtensaMxPic *xtensa_mx_pic_init(unsigned n_extint);
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void xtensa_mx_pic_reset(void *opaque);
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MemoryRegion *xtensa_mx_pic_register_cpu(XtensaMxPic *mx,
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qemu_irq *irq,
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qemu_irq runstall);
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qemu_irq *xtensa_mx_pic_get_extints(XtensaMxPic *mx);
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#endif
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