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qemu-sparc update 

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Merge remote-tracking branch 'remotes/mcayland/tags/qemu-sparc-signed' into staging

qemu-sparc update

# gpg: Signature made Fri 02 Jun 2017 06:09:17 BST
# gpg:                using RSA key 0x5BC2C56FAE0F321F
# gpg: Good signature from "Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>"
# Primary key fingerprint: CC62 1AB9 8E82 200D 915C  C9C4 5BC2 C56F AE0F 321F

* remotes/mcayland/tags/qemu-sparc-signed:
  hw/sparc64: QOM'ify sun4u.c
  hw/sparc: QOM'ify sun4m.c
  hw/timer: QOM'ify slavio_timer
  hw/timer: QOM'ify m48txx_sysbus
  hw/misc: QOM'ify slavio_misc.c
  hw/dma: QOM'ify sun4m_iommu.c
  hw/dma: QOM'ify sparc32_dma.c
  hw/misc: QOM'ify eccmemctl.c

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2017-06-02 15:19:23 +01:00
parent d47a851cae 78fb261db1
commit 1448228af3
8 changed files with 105 additions and 124 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

25
hw/dma/sparc32_dma.c
View File

@ -270,23 +270,28 @@ static const VMStateDescription vmstate_dma = {
}
};
static int sparc32_dma_init1(SysBusDevice *sbd)
static void sparc32_dma_init(Object *obj)
{
DeviceState *dev = DEVICE(sbd);
DMAState *s = SPARC32_DMA(dev);
int reg_size;
DeviceState *dev = DEVICE(obj);
DMAState *s = SPARC32_DMA(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
sysbus_init_irq(sbd, &s->irq);
reg_size = s->is_ledma ? DMA_ETH_SIZE : DMA_SIZE;
memory_region_init_io(&s->iomem, OBJECT(s), &dma_mem_ops, s,
"dma", reg_size);
sysbus_init_mmio(sbd, &s->iomem);
qdev_init_gpio_in(dev, dma_set_irq, 1);
qdev_init_gpio_out(dev, s->gpio, 2);
}
return 0;
static void sparc32_dma_realize(DeviceState *dev, Error **errp)
{
DMAState *s = SPARC32_DMA(dev);
int reg_size;
reg_size = s->is_ledma ? DMA_ETH_SIZE : DMA_SIZE;
memory_region_init_io(&s->iomem, OBJECT(dev), &dma_mem_ops, s,
"dma", reg_size);
}
static Property sparc32_dma_properties[] = {
@ -298,12 +303,11 @@ static Property sparc32_dma_properties[] = {
static void sparc32_dma_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = sparc32_dma_init1;
dc->reset = dma_reset;
dc->vmsd = &vmstate_dma;
dc->props = sparc32_dma_properties;
dc->realize = sparc32_dma_realize;
/* Reason: pointer property "iommu_opaque" */
dc->user_creatable = false;
}
@ -312,6 +316,7 @@ static const TypeInfo sparc32_dma_info = {
.name = TYPE_SPARC32_DMA,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(DMAState),
.instance_init = sparc32_dma_init,
.class_init = sparc32_dma_class_init,
};

12
hw/dma/sun4m_iommu.c
View File

@ -349,17 +349,16 @@ static void iommu_reset(DeviceState *d)
s->regs[IOMMU_MASK_ID] = IOMMU_TS_MASK;
}
static int iommu_init1(SysBusDevice *dev)
static void iommu_init(Object *obj)
{
IOMMUState *s = SUN4M_IOMMU(dev);
IOMMUState *s = SUN4M_IOMMU(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->iomem, OBJECT(s), &iommu_mem_ops, s, "iommu",
memory_region_init_io(&s->iomem, obj, &iommu_mem_ops, s, "iommu",
IOMMU_NREGS * sizeof(uint32_t));
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
static Property iommu_properties[] = {
@ -370,9 +369,7 @@ static Property iommu_properties[] = {
static void iommu_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = iommu_init1;
dc->reset = iommu_reset;
dc->vmsd = &vmstate_iommu;
dc->props = iommu_properties;
@ -382,6 +379,7 @@ static const TypeInfo iommu_info = {
.name = TYPE_SUN4M_IOMMU,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(IOMMUState),
.instance_init = iommu_init,
.class_init = iommu_class_init,
};

25
hw/misc/eccmemctl.c
View File

@ -295,22 +295,29 @@ static void ecc_reset(DeviceState *d)
s->regs[ECC_ECR1] = 0;
}
static int ecc_init1(SysBusDevice *dev)
static void ecc_init(Object *obj)
{
ECCState *s = ECC_MEMCTL(dev);
ECCState *s = ECC_MEMCTL(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
sysbus_init_irq(dev, &s->irq);
s->regs[0] = s->version;
memory_region_init_io(&s->iomem, OBJECT(dev), &ecc_mem_ops, s, "ecc", ECC_SIZE);
memory_region_init_io(&s->iomem, obj, &ecc_mem_ops, s, "ecc", ECC_SIZE);
sysbus_init_mmio(dev, &s->iomem);
}
static void ecc_realize(DeviceState *dev, Error **errp)
{
ECCState *s = ECC_MEMCTL(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
s->regs[0] = s->version;
if (s->version == ECC_MCC) { // SS-600MP only
memory_region_init_io(&s->iomem_diag, OBJECT(dev), &ecc_diag_mem_ops, s,
"ecc.diag", ECC_DIAG_SIZE);
sysbus_init_mmio(dev, &s->iomem_diag);
sysbus_init_mmio(sbd, &s->iomem_diag);
}
return 0;
}
static Property ecc_properties[] = {
@ -321,9 +328,8 @@ static Property ecc_properties[] = {
static void ecc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = ecc_init1;
dc->realize = ecc_realize;
dc->reset = ecc_reset;
dc->vmsd = &vmstate_ecc;
dc->props = ecc_properties;
@ -333,6 +339,7 @@ static const TypeInfo ecc_info = {
.name = TYPE_ECC_MEMCTL,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(ECCState),
.instance_init = ecc_init,
.class_init = ecc_class_init,
};

43
hw/misc/slavio_misc.c
View File

@ -414,76 +414,73 @@ static const VMStateDescription vmstate_misc = {
}
};
static int apc_init1(SysBusDevice *dev)
static void apc_init(Object *obj)
{
APCState *s = APC(dev);
APCState *s = APC(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
sysbus_init_irq(dev, &s->cpu_halt);
/* Power management (APC) XXX: not a Slavio device */
memory_region_init_io(&s->iomem, OBJECT(s), &apc_mem_ops, s,
memory_region_init_io(&s->iomem, obj, &apc_mem_ops, s,
"apc", MISC_SIZE);
sysbus_init_mmio(dev, &s->iomem);
return 0;
}
static int slavio_misc_init1(SysBusDevice *sbd)
static void slavio_misc_init(Object *obj)
{
DeviceState *dev = DEVICE(sbd);
MiscState *s = SLAVIO_MISC(dev);
DeviceState *dev = DEVICE(obj);
MiscState *s = SLAVIO_MISC(obj);
SysBusDevice *sbd = SYS_BUS_DEVICE(obj);
sysbus_init_irq(sbd, &s->irq);
sysbus_init_irq(sbd, &s->fdc_tc);
/* 8 bit registers */
/* Slavio control */
memory_region_init_io(&s->cfg_iomem, OBJECT(s), &slavio_cfg_mem_ops, s,
memory_region_init_io(&s->cfg_iomem, obj, &slavio_cfg_mem_ops, s,
"configuration", MISC_SIZE);
sysbus_init_mmio(sbd, &s->cfg_iomem);
/* Diagnostics */
memory_region_init_io(&s->diag_iomem, OBJECT(s), &slavio_diag_mem_ops, s,
memory_region_init_io(&s->diag_iomem, obj, &slavio_diag_mem_ops, s,
"diagnostic", MISC_SIZE);
sysbus_init_mmio(sbd, &s->diag_iomem);
/* Modem control */
memory_region_init_io(&s->mdm_iomem, OBJECT(s), &slavio_mdm_mem_ops, s,
memory_region_init_io(&s->mdm_iomem, obj, &slavio_mdm_mem_ops, s,
"modem", MISC_SIZE);
sysbus_init_mmio(sbd, &s->mdm_iomem);
/* 16 bit registers */
/* ss600mp diag LEDs */
memory_region_init_io(&s->led_iomem, OBJECT(s), &slavio_led_mem_ops, s,
memory_region_init_io(&s->led_iomem, obj, &slavio_led_mem_ops, s,
"leds", LED_SIZE);
sysbus_init_mmio(sbd, &s->led_iomem);
/* 32 bit registers */
/* System control */
memory_region_init_io(&s->sysctrl_iomem, OBJECT(s), &slavio_sysctrl_mem_ops, s,
memory_region_init_io(&s->sysctrl_iomem, obj, &slavio_sysctrl_mem_ops, s,
"system-control", SYSCTRL_SIZE);
sysbus_init_mmio(sbd, &s->sysctrl_iomem);
/* AUX 1 (Misc System Functions) */
memory_region_init_io(&s->aux1_iomem, OBJECT(s), &slavio_aux1_mem_ops, s,
memory_region_init_io(&s->aux1_iomem, obj, &slavio_aux1_mem_ops, s,
"misc-system-functions", MISC_SIZE);
sysbus_init_mmio(sbd, &s->aux1_iomem);
/* AUX 2 (Software Powerdown Control) */
memory_region_init_io(&s->aux2_iomem, OBJECT(s), &slavio_aux2_mem_ops, s,
memory_region_init_io(&s->aux2_iomem, obj, &slavio_aux2_mem_ops, s,
"software-powerdown-control", MISC_SIZE);
sysbus_init_mmio(sbd, &s->aux2_iomem);
qdev_init_gpio_in(dev, slavio_set_power_fail, 1);
return 0;
}
static void slavio_misc_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = slavio_misc_init1;
dc->reset = slavio_misc_reset;
dc->vmsd = &vmstate_misc;
}
@ -492,21 +489,15 @@ static const TypeInfo slavio_misc_info = {
.name = TYPE_SLAVIO_MISC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MiscState),
.instance_init = slavio_misc_init,
.class_init = slavio_misc_class_init,
};
static void apc_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = apc_init1;
}
static const TypeInfo apc_info = {
.name = TYPE_APC,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(MiscState),
.class_init = apc_class_init,
.instance_init = apc_init,
};
static void slavio_misc_register_types(void)

54
hw/sparc/sun4m.c
View File

@ -585,30 +585,23 @@ typedef struct IDRegState {
MemoryRegion mem;
} IDRegState;
static int idreg_init1(SysBusDevice *dev)
static void idreg_init1(Object *obj)
{
IDRegState *s = MACIO_ID_REGISTER(dev);
IDRegState *s = MACIO_ID_REGISTER(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
memory_region_init_ram(&s->mem, OBJECT(s),
memory_region_init_ram(&s->mem, obj,
"sun4m.idreg", sizeof(idreg_data), &error_fatal);
vmstate_register_ram_global(&s->mem);
memory_region_set_readonly(&s->mem, true);
sysbus_init_mmio(dev, &s->mem);
return 0;
}
static void idreg_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = idreg_init1;
}
static const TypeInfo idreg_info = {
.name = TYPE_MACIO_ID_REGISTER,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(IDRegState),
.class_init = idreg_class_init,
.instance_init = idreg_init1,
};
#define TYPE_TCX_AFX "tcx_afx"
@ -633,28 +626,21 @@ static void afx_init(hwaddr addr)
sysbus_mmio_map(s, 0, addr);
}
static int afx_init1(SysBusDevice *dev)
static void afx_init1(Object *obj)
{
AFXState *s = TCX_AFX(dev);
AFXState *s = TCX_AFX(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4, &error_fatal);
memory_region_init_ram(&s->mem, obj, "sun4m.afx", 4, &error_fatal);
vmstate_register_ram_global(&s->mem);
sysbus_init_mmio(dev, &s->mem);
return 0;
}
static void afx_class_init(ObjectClass *klass, void *data)
{
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = afx_init1;
}
static const TypeInfo afx_info = {
.name = TYPE_TCX_AFX,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(AFXState),
.class_init = afx_class_init,
.instance_init = afx_init1,
};
#define TYPE_OPENPROM "openprom"
@ -707,16 +693,16 @@ static void prom_init(hwaddr addr, const char *bios_name)
}
}
static int prom_init1(SysBusDevice *dev)
static void prom_init1(Object *obj)
{
PROMState *s = OPENPROM(dev);
PROMState *s = OPENPROM(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX,
memory_region_init_ram(&s->prom, obj, "sun4m.prom", PROM_SIZE_MAX,
&error_fatal);
vmstate_register_ram_global(&s->prom);
memory_region_set_readonly(&s->prom, true);
sysbus_init_mmio(dev, &s->prom);
return 0;
}
static Property prom_properties[] = {
@ -726,9 +712,7 @@ static Property prom_properties[] = {
static void prom_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = prom_init1;
dc->props = prom_properties;
}
@ -737,6 +721,7 @@ static const TypeInfo prom_info = {
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PROMState),
.class_init = prom_class_init,
.instance_init = prom_init1,
};
#define TYPE_SUN4M_MEMORY "memory"
@ -750,14 +735,14 @@ typedef struct RamDevice {
} RamDevice;
/* System RAM */
static int ram_init1(SysBusDevice *dev)
static void ram_realize(DeviceState *dev, Error **errp)
{
RamDevice *d = SUN4M_RAM(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
memory_region_allocate_system_memory(&d->ram, OBJECT(d), "sun4m.ram",
d->size);
sysbus_init_mmio(dev, &d->ram);
return 0;
sysbus_init_mmio(sbd, &d->ram);
}
static void ram_init(hwaddr addr, ram_addr_t RAM_size,
@ -793,9 +778,8 @@ static Property ram_properties[] = {
static void ram_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = ram_init1;
dc->realize = ram_realize;
dc->props = ram_properties;
}

20
hw/sparc64/sun4u.c
View File

@ -329,16 +329,16 @@ static void prom_init(hwaddr addr, const char *bios_name)
}
}
static int prom_init1(SysBusDevice *dev)
static void prom_init1(Object *obj)
{
PROMState *s = OPENPROM(dev);
PROMState *s = OPENPROM(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
memory_region_init_ram(&s->prom, OBJECT(s), "sun4u.prom", PROM_SIZE_MAX,
memory_region_init_ram(&s->prom, obj, "sun4u.prom", PROM_SIZE_MAX,
&error_fatal);
vmstate_register_ram_global(&s->prom);
memory_region_set_readonly(&s->prom, true);
sysbus_init_mmio(dev, &s->prom);
return 0;
}
static Property prom_properties[] = {
@ -348,9 +348,7 @@ static Property prom_properties[] = {
static void prom_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = prom_init1;
dc->props = prom_properties;
}
@ -359,6 +357,7 @@ static const TypeInfo prom_info = {
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(PROMState),
.class_init = prom_class_init,
.instance_init = prom_init1,
};
@ -373,15 +372,15 @@ typedef struct RamDevice {
} RamDevice;
/* System RAM */
static int ram_init1(SysBusDevice *dev)
static void ram_realize(DeviceState *dev, Error **errp)
{
RamDevice *d = SUN4U_RAM(dev);
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
memory_region_init_ram(&d->ram, OBJECT(d), "sun4u.ram", d->size,
&error_fatal);
vmstate_register_ram_global(&d->ram);
sysbus_init_mmio(dev, &d->ram);
return 0;
sysbus_init_mmio(sbd, &d->ram);
}
static void ram_init(hwaddr addr, ram_addr_t RAM_size)
@ -409,9 +408,8 @@ static Property ram_properties[] = {
static void ram_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = ram_init1;
dc->realize = ram_realize;
dc->props = ram_properties;
}

38
hw/timer/m48t59.c
View File

@ -640,34 +640,33 @@ void m48t59_realize_common(M48t59State *s, Error **errp)
s->wd_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &watchdog_cb, s);
}
qemu_get_timedate(&s->alarm, 0);
vmstate_register(NULL, -1, &vmstate_m48t59, s);
}
static int m48t59_init1(SysBusDevice *dev)
static void m48t59_init1(Object *obj)
{
M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_GET_CLASS(dev);
M48txxSysBusState *d = M48TXX_SYS_BUS(dev);
Object *o = OBJECT(dev);
M48txxSysBusDeviceClass *u = M48TXX_SYS_BUS_GET_CLASS(obj);
M48txxSysBusState *d = M48TXX_SYS_BUS(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
M48t59State *s = &d->state;
Error *err = NULL;
s->model = u->info.model;
s->size = u->info.size;
sysbus_init_irq(dev, &s->IRQ);
memory_region_init_io(&s->iomem, o, &nvram_ops, s, "m48t59.nvram",
memory_region_init_io(&s->iomem, obj, &nvram_ops, s, "m48t59.nvram",
s->size);
memory_region_init_io(&d->io, o, &m48t59_io_ops, s, "m48t59", 4);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_mmio(dev, &d->io);
m48t59_realize_common(s, &err);
if (err != NULL) {
error_free(err);
return -1;
}
memory_region_init_io(&d->io, obj, &m48t59_io_ops, s, "m48t59", 4);
}
return 0;
static void m48t59_realize(DeviceState *dev, Error **errp)
{
M48txxSysBusState *d = M48TXX_SYS_BUS(dev);
M48t59State *s = &d->state;
SysBusDevice *sbd = SYS_BUS_DEVICE(dev);
sysbus_init_mmio(sbd, &s->iomem);
sysbus_init_mmio(sbd, &d->io);
m48t59_realize_common(s, errp);
}
static uint32_t m48txx_sysbus_read(Nvram *obj, uint32_t addr)
@ -696,12 +695,12 @@ static Property m48t59_sysbus_properties[] = {
static void m48txx_sysbus_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
NvramClass *nc = NVRAM_CLASS(klass);
k->init = m48t59_init1;
dc->realize = m48t59_realize;
dc->reset = m48t59_reset_sysbus;
dc->props = m48t59_sysbus_properties;
dc->vmsd = &vmstate_m48t59;
nc->read = m48txx_sysbus_read;
nc->write = m48txx_sysbus_write;
nc->toggle_lock = m48txx_sysbus_toggle_lock;
@ -725,6 +724,7 @@ static const TypeInfo m48txx_sysbus_type_info = {
.name = TYPE_M48TXX_SYS_BUS,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(M48txxSysBusState),
.instance_init = m48t59_init1,
.abstract = true,
.class_init = m48txx_sysbus_class_init,
.interfaces = (InterfaceInfo[]) {

12
hw/timer/slavio_timer.c
View File

@ -373,9 +373,10 @@ static void slavio_timer_reset(DeviceState *d)
s->cputimer_mode = 0;
}
static int slavio_timer_init1(SysBusDevice *dev)
static void slavio_timer_init(Object *obj)
{
SLAVIO_TIMERState *s = SLAVIO_TIMER(dev);
SLAVIO_TIMERState *s = SLAVIO_TIMER(obj);
SysBusDevice *dev = SYS_BUS_DEVICE(obj);
QEMUBH *bh;
unsigned int i;
TimerContext *tc;
@ -394,14 +395,12 @@ static int slavio_timer_init1(SysBusDevice *dev)
size = i == 0 ? SYS_TIMER_SIZE : CPU_TIMER_SIZE;
snprintf(timer_name, sizeof(timer_name), "timer-%i", i);
memory_region_init_io(&tc->iomem, OBJECT(s), &slavio_timer_mem_ops, tc,
memory_region_init_io(&tc->iomem, obj, &slavio_timer_mem_ops, tc,
timer_name, size);
sysbus_init_mmio(dev, &tc->iomem);
sysbus_init_irq(dev, &s->cputimer[i].irq);
}
return 0;
}
static Property slavio_timer_properties[] = {
@ -412,9 +411,7 @@ static Property slavio_timer_properties[] = {
static void slavio_timer_class_init(ObjectClass *klass, void *data)
{
DeviceClass *dc = DEVICE_CLASS(klass);
SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
k->init = slavio_timer_init1;
dc->reset = slavio_timer_reset;
dc->vmsd = &vmstate_slavio_timer;
dc->props = slavio_timer_properties;
@ -424,6 +421,7 @@ static const TypeInfo slavio_timer_info = {
.name = TYPE_SLAVIO_TIMER,
.parent = TYPE_SYS_BUS_DEVICE,
.instance_size = sizeof(SLAVIO_TIMERState),
.instance_init = slavio_timer_init,
.class_init = slavio_timer_class_init,
};