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target/arm: Create gen_gvec_{qrdmla,qrdmls} 

Provide a functional interface for the vector expansion.
This fits better with the existing set of helpers that
we provide for other operations.

Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20200513163245.17915-13-richard.henderson@linaro.org
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson 2020-05-13 09:32:41 -07:00 committed by Peter Maydell
parent fe6fb4beb2
commit 146aa66ce5
3 changed files with 34 additions and 59 deletions
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34
target/arm/translate-a64.c
View File

@ -587,18 +587,6 @@ static void gen_gvec_op3_ool(DisasContext *s, bool is_q, int rd,
is_q ? 16 : 8, vec_full_reg_size(s), data, fn);
}
/* Expand a 3-operand + env pointer operation using
* an out-of-line helper.
*/
static void gen_gvec_op3_env(DisasContext *s, bool is_q, int rd,
int rn, int rm, gen_helper_gvec_3_ptr *fn)
{
tcg_gen_gvec_3_ptr(vec_full_reg_offset(s, rd),
vec_full_reg_offset(s, rn),
vec_full_reg_offset(s, rm), cpu_env,
is_q ? 16 : 8, vec_full_reg_size(s), 0, fn);
}
/* Expand a 3-operand + fpstatus pointer + simd data value operation using
* an out-of-line helper.
*/
@ -11693,29 +11681,11 @@ static void disas_simd_three_reg_same_extra(DisasContext *s, uint32_t insn)
switch (opcode) {
case 0x0: /* SQRDMLAH (vector) */
switch (size) {
case 1:
gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s16);
break;
case 2:
gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlah_s32);
break;
default:
g_assert_not_reached();
}
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqrdmlah_qc, size);
return;
case 0x1: /* SQRDMLSH (vector) */
switch (size) {
case 1:
gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s16);
break;
case 2:
gen_gvec_op3_env(s, is_q, rd, rn, rm, gen_helper_gvec_qrdmlsh_s32);
break;
default:
g_assert_not_reached();
}
gen_gvec_fn3(s, is_q, rd, rn, rm, gen_gvec_sqrdmlsh_qc, size);
return;
case 0x2: /* SDOT / UDOT */

54
target/arm/translate.c
View File

@ -3629,20 +3629,26 @@ static const uint8_t neon_2rm_sizes[] = {
[NEON_2RM_VCVT_UF] = 0x4,
};
/* Expand v8.1 simd helper. */
static int do_v81_helper(DisasContext *s, gen_helper_gvec_3_ptr *fn,
int q, int rd, int rn, int rm)
void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz)
{
if (dc_isar_feature(aa32_rdm, s)) {
int opr_sz = (1 + q) * 8;
tcg_gen_gvec_3_ptr(vfp_reg_offset(1, rd),
vfp_reg_offset(1, rn),
vfp_reg_offset(1, rm), cpu_env,
opr_sz, opr_sz, 0, fn);
return 0;
}
return 1;
static gen_helper_gvec_3_ptr * const fns[2] = {
gen_helper_gvec_qrdmlah_s16, gen_helper_gvec_qrdmlah_s32
};
tcg_debug_assert(vece >= 1 && vece <= 2);
tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, cpu_env,
opr_sz, max_sz, 0, fns[vece - 1]);
}
void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz)
{
static gen_helper_gvec_3_ptr * const fns[2] = {
gen_helper_gvec_qrdmlsh_s16, gen_helper_gvec_qrdmlsh_s32
};
tcg_debug_assert(vece >= 1 && vece <= 2);
tcg_gen_gvec_3_ptr(rd_ofs, rn_ofs, rm_ofs, cpu_env,
opr_sz, max_sz, 0, fns[vece - 1]);
}
#define GEN_CMP0(NAME, COND) \
@ -5197,13 +5203,10 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
break; /* VPADD */
}
/* VQRDMLAH */
switch (size) {
case 1:
return do_v81_helper(s, gen_helper_gvec_qrdmlah_s16,
q, rd, rn, rm);
case 2:
return do_v81_helper(s, gen_helper_gvec_qrdmlah_s32,
q, rd, rn, rm);
if (dc_isar_feature(aa32_rdm, s) && (size == 1 || size == 2)) {
gen_gvec_sqrdmlah_qc(size, rd_ofs, rn_ofs, rm_ofs,
vec_size, vec_size);
return 0;
}
return 1;
@ -5216,13 +5219,10 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
break;
}
/* VQRDMLSH */
switch (size) {
case 1:
return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s16,
q, rd, rn, rm);
case 2:
return do_v81_helper(s, gen_helper_gvec_qrdmlsh_s32,
q, rd, rn, rm);
if (dc_isar_feature(aa32_rdm, s) && (size == 1 || size == 2)) {
gen_gvec_sqrdmlsh_qc(size, rd_ofs, rn_ofs, rm_ofs,
vec_size, vec_size);
return 0;
}
return 1;

5
target/arm/translate.h
View File

@ -332,6 +332,11 @@ void gen_gvec_sri(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
void gen_gvec_sli(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
int64_t shift, uint32_t opr_sz, uint32_t max_sz);
void gen_gvec_sqrdmlah_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
void gen_gvec_sqrdmlsh_qc(unsigned vece, uint32_t rd_ofs, uint32_t rn_ofs,
uint32_t rm_ofs, uint32_t opr_sz, uint32_t max_sz);
/*
* Forward to the isar_feature_* tests given a DisasContext pointer.
*/