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target/microblaze: Add the unaligned-exceptions property 

Add the unaligned-exceptions property to control if the core
traps unaligned memory accesses.

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Reviewed-by: Luc Michel <luc.michel@greensocs.com>
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
This commit is contained in:
Edgar E. Iglesias 2019-10-30 14:09:37 +01:00
parent 622cc7305c
commit 1507e5f62e
3 changed files with 7 additions and 2 deletions
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4
target/microblaze/cpu.c
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@ -211,6 +211,8 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp)
PVR2_DIV_ZERO_EXC_MASK : 0) |
(cpu->cfg.illegal_opcode_exception ?
PVR2_ILL_OPCODE_EXC_MASK : 0) |
(cpu->cfg.unaligned_exceptions ?
PVR2_UNALIGNED_EXC_MASK : 0) |
(cpu->cfg.opcode_0_illegal ?
PVR2_OPCODE_0x0_ILL_MASK : 0);
@ -284,6 +286,8 @@ static Property mb_properties[] = {
cfg.illegal_opcode_exception, false),
DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU,
cfg.div_zero_exception, false),
DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU,
cfg.unaligned_exceptions, false),
DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU,
cfg.opcode_0_illegal, false),
DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version),

1
target/microblaze/cpu.h
View File

@ -306,6 +306,7 @@ struct MicroBlazeCPU {
bool illegal_opcode_exception;
bool opcode_0_illegal;
bool div_zero_exception;
bool unaligned_exceptions;
char *version;
uint8_t pvr;
} cfg;

4
target/microblaze/translate.c
View File

@ -995,7 +995,7 @@ static void dec_load(DisasContext *dc)
v = tcg_temp_new_i32();
tcg_gen_qemu_ld_i32(v, addr, mem_index, mop);
if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
TCGv_i32 t0 = tcg_const_i32(0);
TCGv_i32 treg = tcg_const_i32(dc->rd);
TCGv_i32 tsize = tcg_const_i32(size - 1);
@ -1110,7 +1110,7 @@ static void dec_store(DisasContext *dc)
tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop);
/* Verify alignment if needed. */
if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) {
if (dc->cpu->cfg.unaligned_exceptions && size > 1) {
TCGv_i32 t1 = tcg_const_i32(1);
TCGv_i32 treg = tcg_const_i32(dc->rd);
TCGv_i32 tsize = tcg_const_i32(size - 1);