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hw/intc/arm_gicv3: Set GICR_CTLR.CES if LPIs are supported 

The GICR_CTLR.CES bit is a read-only bit which is set to 1 to indicate
that the GICR_CTLR.EnableLPIs bit can be written to 0 to disable
LPIs (as opposed to allowing LPIs to be enabled but not subsequently
disabled). Our implementation permits this, so advertise it
by setting CES to 1.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20220122182444.724087-10-peter.maydell@linaro.org
This commit is contained in:
Peter Maydell 2022-01-22 18:24:39 +00:00
parent d7d19c0aeb
commit 1611956bce
2 changed files with 5 additions and 0 deletions
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4
hw/intc/arm_gicv3_common.c
View File

@ -429,6 +429,10 @@ static void arm_gicv3_common_reset(DeviceState *dev)
cs->level = 0;
cs->gicr_ctlr = 0;
if (s->lpi_enable) {
/* Our implementation supports clearing GICR_CTLR.EnableLPIs */
cs->gicr_ctlr |= GICR_CTLR_CES;
}
cs->gicr_statusr[GICV3_S] = 0;
cs->gicr_statusr[GICV3_NS] = 0;
cs->gicr_waker = GICR_WAKER_ProcessorSleep | GICR_WAKER_ChildrenAsleep;

1
hw/intc/gicv3_internal.h
View File

@ -110,6 +110,7 @@
#define GICR_NSACR (GICR_SGI_OFFSET + 0x0E00)
#define GICR_CTLR_ENABLE_LPIS (1U << 0)
#define GICR_CTLR_CES (1U << 1)
#define GICR_CTLR_RWP (1U << 3)
#define GICR_CTLR_DPG0 (1U << 24)
#define GICR_CTLR_DPG1NS (1U << 25)