mirror of https://gitee.com/openkylin/qemu.git
tcg/i386: Support vector absolute value
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
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@ -182,7 +182,7 @@ extern bool have_avx2;
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#define TCG_TARGET_HAS_orc_vec 0
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#define TCG_TARGET_HAS_not_vec 0
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#define TCG_TARGET_HAS_neg_vec 0
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#define TCG_TARGET_HAS_abs_vec 0
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#define TCG_TARGET_HAS_abs_vec 1
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#define TCG_TARGET_HAS_shi_vec 1
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#define TCG_TARGET_HAS_shs_vec 1
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#define TCG_TARGET_HAS_shv_vec have_avx2
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@ -369,6 +369,9 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
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#define OPC_MOVSLQ (0x63 | P_REXW)
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#define OPC_MOVZBL (0xb6 | P_EXT)
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#define OPC_MOVZWL (0xb7 | P_EXT)
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#define OPC_PABSB (0x1c | P_EXT38 | P_DATA16)
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#define OPC_PABSW (0x1d | P_EXT38 | P_DATA16)
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#define OPC_PABSD (0x1e | P_EXT38 | P_DATA16)
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#define OPC_PACKSSDW (0x6b | P_EXT | P_DATA16)
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#define OPC_PACKSSWB (0x63 | P_EXT | P_DATA16)
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#define OPC_PACKUSDW (0x2b | P_EXT38 | P_DATA16)
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@ -2741,6 +2744,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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static int const sars_insn[4] = {
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OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_UD2
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};
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static int const abs_insn[4] = {
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/* TODO: AVX512 adds support for MO_64. */
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OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_UD2
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};
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TCGType type = vecl + TCG_TYPE_V64;
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int insn, sub;
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@ -2829,6 +2836,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
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insn = OPC_PUNPCKLDQ;
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goto gen_simd;
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#endif
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case INDEX_op_abs_vec:
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insn = abs_insn[vece];
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a2 = a1;
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a1 = 0;
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goto gen_simd;
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gen_simd:
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tcg_debug_assert(insn != OPC_UD2);
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if (type == TCG_TYPE_V256) {
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@ -3206,6 +3218,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
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case INDEX_op_dup2_vec:
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#endif
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return &x_x_x;
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case INDEX_op_abs_vec:
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case INDEX_op_dup_vec:
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case INDEX_op_shli_vec:
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case INDEX_op_shri_vec:
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@ -3283,6 +3296,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
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case INDEX_op_umin_vec:
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case INDEX_op_umax_vec:
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return vece <= MO_32 ? 1 : -1;
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case INDEX_op_abs_vec:
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return vece <= MO_32;
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default:
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return 0;
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