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tcg/i386: Support vector absolute value 

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
This commit is contained in:
Richard Henderson 2019-04-17 15:54:20 -10:00
parent bcefc90208
commit 18f9b65f1a
2 changed files with 16 additions and 1 deletions
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2
tcg/i386/tcg-target.h
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@ -182,7 +182,7 @@ extern bool have_avx2;
#define TCG_TARGET_HAS_orc_vec 0 #define TCG_TARGET_HAS_orc_vec 0
#define TCG_TARGET_HAS_not_vec 0 #define TCG_TARGET_HAS_not_vec 0
#define TCG_TARGET_HAS_neg_vec 0 #define TCG_TARGET_HAS_neg_vec 0
#define TCG_TARGET_HAS_abs_vec 0 #define TCG_TARGET_HAS_abs_vec 1
#define TCG_TARGET_HAS_shi_vec 1 #define TCG_TARGET_HAS_shi_vec 1
#define TCG_TARGET_HAS_shs_vec 1 #define TCG_TARGET_HAS_shs_vec 1
#define TCG_TARGET_HAS_shv_vec have_avx2 #define TCG_TARGET_HAS_shv_vec have_avx2

15
tcg/i386/tcg-target.inc.c
View File

@ -369,6 +369,9 @@ static inline int tcg_target_const_match(tcg_target_long val, TCGType type,
#define OPC_MOVSLQ (0x63 | P_REXW) #define OPC_MOVSLQ (0x63 | P_REXW)
#define OPC_MOVZBL (0xb6 | P_EXT) #define OPC_MOVZBL (0xb6 | P_EXT)
#define OPC_MOVZWL (0xb7 | P_EXT) #define OPC_MOVZWL (0xb7 | P_EXT)
#define OPC_PABSB (0x1c | P_EXT38 | P_DATA16)
#define OPC_PABSW (0x1d | P_EXT38 | P_DATA16)
#define OPC_PABSD (0x1e | P_EXT38 | P_DATA16)
#define OPC_PACKSSDW (0x6b | P_EXT | P_DATA16) #define OPC_PACKSSDW (0x6b | P_EXT | P_DATA16)
#define OPC_PACKSSWB (0x63 | P_EXT | P_DATA16) #define OPC_PACKSSWB (0x63 | P_EXT | P_DATA16)
#define OPC_PACKUSDW (0x2b | P_EXT38 | P_DATA16) #define OPC_PACKUSDW (0x2b | P_EXT38 | P_DATA16)
@ -2741,6 +2744,10 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
static int const sars_insn[4] = { static int const sars_insn[4] = {
OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_UD2 OPC_UD2, OPC_PSRAW, OPC_PSRAD, OPC_UD2
}; };
static int const abs_insn[4] = {
/* TODO: AVX512 adds support for MO_64. */
OPC_PABSB, OPC_PABSW, OPC_PABSD, OPC_UD2
};
TCGType type = vecl + TCG_TYPE_V64; TCGType type = vecl + TCG_TYPE_V64;
int insn, sub; int insn, sub;
@ -2829,6 +2836,11 @@ static void tcg_out_vec_op(TCGContext *s, TCGOpcode opc,
insn = OPC_PUNPCKLDQ; insn = OPC_PUNPCKLDQ;
goto gen_simd; goto gen_simd;
#endif #endif
case INDEX_op_abs_vec:
insn = abs_insn[vece];
a2 = a1;
a1 = 0;
goto gen_simd;
gen_simd: gen_simd:
tcg_debug_assert(insn != OPC_UD2); tcg_debug_assert(insn != OPC_UD2);
if (type == TCG_TYPE_V256) { if (type == TCG_TYPE_V256) {
@ -3206,6 +3218,7 @@ static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op)
case INDEX_op_dup2_vec: case INDEX_op_dup2_vec:
#endif #endif
return &x_x_x; return &x_x_x;
case INDEX_op_abs_vec:
case INDEX_op_dup_vec: case INDEX_op_dup_vec:
case INDEX_op_shli_vec: case INDEX_op_shli_vec:
case INDEX_op_shri_vec: case INDEX_op_shri_vec:
@ -3283,6 +3296,8 @@ int tcg_can_emit_vec_op(TCGOpcode opc, TCGType type, unsigned vece)
case INDEX_op_umin_vec: case INDEX_op_umin_vec:
case INDEX_op_umax_vec: case INDEX_op_umax_vec:
return vece <= MO_32 ? 1 : -1; return vece <= MO_32 ? 1 : -1;
case INDEX_op_abs_vec:
return vece <= MO_32;
default: default:
return 0; return 0;