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TileGX basic instructions 

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Merge remote-tracking branch 'remotes/rth/tags/pull-tile-20150915' into staging

TileGX basic instructions

# gpg: Signature made Tue 15 Sep 2015 15:57:08 BST using RSA key ID 4DD0279B
# gpg: Good signature from "Richard Henderson <rth7680@gmail.com>"
# gpg:                 aka "Richard Henderson <rth@redhat.com>"
# gpg:                 aka "Richard Henderson <rth@twiddle.net>"

* remotes/rth/tags/pull-tile-20150915: (35 commits)
  target-tilegx: Handle v1shl, v1shru, v1shrs
  target-tilegx: Handle v1shli, v1shrui
  target-tilegx: Handle v4int_l/h
  target-tilegx: Handle atomic instructions
  target-tilegx: Handle mtspr, mfspr
  target-tilegx: Handle v1cmpeq, v1cmpne
  target-tilegx: Handle mask instructions
  target-tilegx: Handle scalar multiply instructions
  target-tilegx: Handle conditional move instructions
  target-tilegx: Handle shift instructions
  target-tilegx: Handle bitfield instructions
  target-tilegx: Implement system and memory management instructions
  target-tilegx: Handle comparison instructions
  target-tilegx: Handle conditional branch instructions
  target-tilegx: Handle unconditional jump instructions
  target-tilegx: Handle post-increment load and store instructions
  target-tilegx: Handle basic load and store instructions
  target-tilegx: Handle most bit manipulation instructions
  target-arm: Use new revbit functions
  host-utils: Add revbit functions
  ...

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell 2015-09-15 17:24:27 +01:00
parent 619622424d 461aa6783e
commit 1a3abef74b
25 changed files with 5431 additions and 31 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
configure vendored
View File

@ -5441,6 +5441,8 @@ case "$target_name" in
s390x)
gdb_xml_files="s390x-core64.xml s390-acr.xml s390-fpr.xml s390-vx.xml s390-cr.xml"
;;
tilegx)
;;
tricore)
;;
unicore32)

1
default-configs/tilegx-linux-user.mak Normal file
View File

@ -0,0 +1 @@
# Default configuration for tilegx-linux-user

2
include/elf.h
View File

@ -133,6 +133,8 @@ typedef int64_t Elf64_Sxword;
#define EM_AARCH64 183
#define EM_TILEGX 191 /* TILE-Gx */
/* This is the info that is needed to parse the dynamic section of the file */
#define DT_NULL 0
#define DT_NEEDED 1

77
include/qemu/host-utils.h
View File

@ -26,6 +26,7 @@
#define HOST_UTILS_H 1
#include "qemu/compiler.h" /* QEMU_GNUC_PREREQ */
#include "qemu/bswap.h"
#include <limits.h>
#include <stdbool.h>
@ -391,6 +392,80 @@ static inline int ctpop64(uint64_t val)
#endif
}
/**
* revbit8 - reverse the bits in an 8-bit value.
* @x: The value to modify.
*/
static inline uint8_t revbit8(uint8_t x)
{
/* Assign the correct nibble position. */
x = ((x & 0xf0) >> 4)
| ((x & 0x0f) << 4);
/* Assign the correct bit position. */
x = ((x & 0x88) >> 3)
| ((x & 0x44) >> 1)
| ((x & 0x22) << 1)
| ((x & 0x11) << 3);
return x;
}
/**
* revbit16 - reverse the bits in a 16-bit value.
* @x: The value to modify.
*/
static inline uint16_t revbit16(uint16_t x)
{
/* Assign the correct byte position. */
x = bswap16(x);
/* Assign the correct nibble position. */
x = ((x & 0xf0f0) >> 4)
| ((x & 0x0f0f) << 4);
/* Assign the correct bit position. */
x = ((x & 0x8888) >> 3)
| ((x & 0x4444) >> 1)
| ((x & 0x2222) << 1)
| ((x & 0x1111) << 3);
return x;
}
/**
* revbit32 - reverse the bits in a 32-bit value.
* @x: The value to modify.
*/
static inline uint32_t revbit32(uint32_t x)
{
/* Assign the correct byte position. */
x = bswap32(x);
/* Assign the correct nibble position. */
x = ((x & 0xf0f0f0f0u) >> 4)
| ((x & 0x0f0f0f0fu) << 4);
/* Assign the correct bit position. */
x = ((x & 0x88888888u) >> 3)
| ((x & 0x44444444u) >> 1)
| ((x & 0x22222222u) << 1)
| ((x & 0x11111111u) << 3);
return x;
}
/**
* revbit64 - reverse the bits in a 64-bit value.
* @x: The value to modify.
*/
static inline uint64_t revbit64(uint64_t x)
{
/* Assign the correct byte position. */
x = bswap64(x);
/* Assign the correct nibble position. */
x = ((x & 0xf0f0f0f0f0f0f0f0ull) >> 4)
| ((x & 0x0f0f0f0f0f0f0f0full) << 4);
/* Assign the correct bit position. */
x = ((x & 0x8888888888888888ull) >> 3)
| ((x & 0x4444444444444444ull) >> 1)
| ((x & 0x2222222222222222ull) << 1)
| ((x & 0x1111111111111111ull) << 3);
return x;
}
/* Host type specific sizes of these routines. */
#if ULONG_MAX == UINT32_MAX
@ -399,12 +474,14 @@ static inline int ctpop64(uint64_t val)
# define clol clo32
# define ctol cto32
# define ctpopl ctpop32
# define revbitl revbit32
#elif ULONG_MAX == UINT64_MAX
# define clzl clz64
# define ctzl ctz64
# define clol clo64
# define ctol cto64
# define ctpopl ctpop64
# define revbitl revbit64
#else
# error Unknown sizeof long
#endif

23
linux-user/elfload.c
View File

@ -1218,6 +1218,29 @@ static inline void init_thread(struct target_pt_regs *regs, struct image_info *i
#endif /* TARGET_S390X */
#ifdef TARGET_TILEGX
/* 42 bits real used address, a half for user mode */
#define ELF_START_MMAP (0x00000020000000000ULL)
#define elf_check_arch(x) ((x) == EM_TILEGX)
#define ELF_CLASS ELFCLASS64
#define ELF_DATA ELFDATA2LSB
#define ELF_ARCH EM_TILEGX
static inline void init_thread(struct target_pt_regs *regs,
struct image_info *infop)
{
regs->pc = infop->entry;
regs->sp = infop->start_stack;
}
#define ELF_EXEC_PAGESIZE 65536 /* TILE-Gx page size is 64KB */
#endif /* TARGET_TILEGX */
#ifndef ELF_PLATFORM
#define ELF_PLATFORM (NULL)
#endif

238
linux-user/main.c
View File

@ -3412,6 +3412,233 @@ void cpu_loop(CPUS390XState *env)
#endif /* TARGET_S390X */
#ifdef TARGET_TILEGX
static void gen_sigsegv_maperr(CPUTLGState *env, target_ulong addr)
{
target_siginfo_t info;
info.si_signo = TARGET_SIGSEGV;
info.si_errno = 0;
info.si_code = TARGET_SEGV_MAPERR;
info._sifields._sigfault._addr = addr;
queue_signal(env, info.si_signo, &info);
}
static void gen_sigill_reg(CPUTLGState *env)
{
target_siginfo_t info;
info.si_signo = TARGET_SIGILL;
info.si_errno = 0;
info.si_code = TARGET_ILL_PRVREG;
info._sifields._sigfault._addr = env->pc;
queue_signal(env, info.si_signo, &info);
}
static void set_regval(CPUTLGState *env, uint8_t reg, uint64_t val)
{
if (unlikely(reg >= TILEGX_R_COUNT)) {
switch (reg) {
case TILEGX_R_SN:
case TILEGX_R_ZERO:
return;
case TILEGX_R_IDN0:
case TILEGX_R_IDN1:
case TILEGX_R_UDN0:
case TILEGX_R_UDN1:
case TILEGX_R_UDN2:
case TILEGX_R_UDN3:
gen_sigill_reg(env);
return;
default:
g_assert_not_reached();
}
}
env->regs[reg] = val;
}
/*
* Compare the 8-byte contents of the CmpValue SPR with the 8-byte value in
* memory at the address held in the first source register. If the values are
* not equal, then no memory operation is performed. If the values are equal,
* the 8-byte quantity from the second source register is written into memory
* at the address held in the first source register. In either case, the result
* of the instruction is the value read from memory. The compare and write to
* memory are atomic and thus can be used for synchronization purposes. This
* instruction only operates for addresses aligned to a 8-byte boundary.
* Unaligned memory access causes an Unaligned Data Reference interrupt.
*
* Functional Description (64-bit)
* uint64_t memVal = memoryReadDoubleWord (rf[SrcA]);
* rf[Dest] = memVal;
* if (memVal == SPR[CmpValueSPR])
* memoryWriteDoubleWord (rf[SrcA], rf[SrcB]);
*
* Functional Description (32-bit)
* uint64_t memVal = signExtend32 (memoryReadWord (rf[SrcA]));
* rf[Dest] = memVal;
* if (memVal == signExtend32 (SPR[CmpValueSPR]))
* memoryWriteWord (rf[SrcA], rf[SrcB]);
*
*
* This function also processes exch and exch4 which need not process SPR.
*/
static void do_exch(CPUTLGState *env, bool quad, bool cmp)
{
target_ulong addr;
target_long val, sprval;
start_exclusive();
addr = env->atomic_srca;
if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
goto sigsegv_maperr;
}
if (cmp) {
if (quad) {
sprval = env->spregs[TILEGX_SPR_CMPEXCH];
} else {
sprval = sextract64(env->spregs[TILEGX_SPR_CMPEXCH], 0, 32);
}
}
if (!cmp || val == sprval) {
target_long valb = env->atomic_srcb;
if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
goto sigsegv_maperr;
}
}
set_regval(env, env->atomic_dstr, val);
end_exclusive();
return;
sigsegv_maperr:
end_exclusive();
gen_sigsegv_maperr(env, addr);
}
static void do_fetch(CPUTLGState *env, int trapnr, bool quad)
{
int8_t write = 1;
target_ulong addr;
target_long val, valb;
start_exclusive();
addr = env->atomic_srca;
valb = env->atomic_srcb;
if (quad ? get_user_s64(val, addr) : get_user_s32(val, addr)) {
goto sigsegv_maperr;
}
switch (trapnr) {
case TILEGX_EXCP_OPCODE_FETCHADD:
case TILEGX_EXCP_OPCODE_FETCHADD4:
valb += val;
break;
case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
valb += val;
if (valb < 0) {
write = 0;
}
break;
case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
valb += val;
if ((int32_t)valb < 0) {
write = 0;
}
break;
case TILEGX_EXCP_OPCODE_FETCHAND:
case TILEGX_EXCP_OPCODE_FETCHAND4:
valb &= val;
break;
case TILEGX_EXCP_OPCODE_FETCHOR:
case TILEGX_EXCP_OPCODE_FETCHOR4:
valb |= val;
break;
default:
g_assert_not_reached();
}
if (write) {
if (quad ? put_user_u64(valb, addr) : put_user_u32(valb, addr)) {
goto sigsegv_maperr;
}
}
set_regval(env, env->atomic_dstr, val);
end_exclusive();
return;
sigsegv_maperr:
end_exclusive();
gen_sigsegv_maperr(env, addr);
}
void cpu_loop(CPUTLGState *env)
{
CPUState *cs = CPU(tilegx_env_get_cpu(env));
int trapnr;
while (1) {
cpu_exec_start(cs);
trapnr = cpu_tilegx_exec(cs);
cpu_exec_end(cs);
switch (trapnr) {
case TILEGX_EXCP_SYSCALL:
env->regs[TILEGX_R_RE] = do_syscall(env, env->regs[TILEGX_R_NR],
env->regs[0], env->regs[1],
env->regs[2], env->regs[3],
env->regs[4], env->regs[5],
env->regs[6], env->regs[7]);
env->regs[TILEGX_R_ERR] = TILEGX_IS_ERRNO(env->regs[TILEGX_R_RE])
? - env->regs[TILEGX_R_RE]
: 0;
break;
case TILEGX_EXCP_OPCODE_EXCH:
do_exch(env, true, false);
break;
case TILEGX_EXCP_OPCODE_EXCH4:
do_exch(env, false, false);
break;
case TILEGX_EXCP_OPCODE_CMPEXCH:
do_exch(env, true, true);
break;
case TILEGX_EXCP_OPCODE_CMPEXCH4:
do_exch(env, false, true);
break;
case TILEGX_EXCP_OPCODE_FETCHADD:
case TILEGX_EXCP_OPCODE_FETCHADDGEZ:
case TILEGX_EXCP_OPCODE_FETCHAND:
case TILEGX_EXCP_OPCODE_FETCHOR:
do_fetch(env, trapnr, true);
break;
case TILEGX_EXCP_OPCODE_FETCHADD4:
case TILEGX_EXCP_OPCODE_FETCHADDGEZ4:
case TILEGX_EXCP_OPCODE_FETCHAND4:
case TILEGX_EXCP_OPCODE_FETCHOR4:
do_fetch(env, trapnr, false);
break;
case TILEGX_EXCP_REG_IDN_ACCESS:
case TILEGX_EXCP_REG_UDN_ACCESS:
gen_sigill_reg(env);
break;
case TILEGX_EXCP_SEGV:
gen_sigsegv_maperr(env, env->excaddr);
break;
default:
fprintf(stderr, "trapnr is %d[0x%x].\n", trapnr, trapnr);
g_assert_not_reached();
}
process_pending_signals(env);
}
}
#endif
THREAD CPUState *thread_cpu;
void task_settid(TaskState *ts)
@ -4377,6 +4604,17 @@ int main(int argc, char **argv, char **envp)
env->psw.mask = regs->psw.mask;
env->psw.addr = regs->psw.addr;
}
#elif defined(TARGET_TILEGX)
{
int i;
for (i = 0; i < TILEGX_R_COUNT; i++) {
env->regs[i] = regs->regs[i];
}
for (i = 0; i < TILEGX_SPR_COUNT; i++) {
env->spregs[i] = 0;
}
env->pc = regs->pc;
}
#else
#error unsupported target CPU
#endif

50
linux-user/syscall.c
View File

@ -213,7 +213,7 @@ static int gettid(void) {
return -ENOSYS;
}
#endif
#ifdef __NR_getdents
#if defined(TARGET_NR_getdents) && defined(__NR_getdents)
_syscall3(int, sys_getdents, uint, fd, struct linux_dirent *, dirp, uint, count);
#endif
#if !defined(__NR_getdents) || \
@ -5640,6 +5640,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = get_errno(write(arg1, p, arg3));
unlock_user(p, arg2, 0);
break;
#ifdef TARGET_NR_open
case TARGET_NR_open:
if (!(p = lock_user_string(arg1)))
goto efault;
@ -5648,6 +5649,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
arg3));
unlock_user(p, arg1, 0);
break;
#endif
case TARGET_NR_openat:
if (!(p = lock_user_string(arg2)))
goto efault;
@ -5662,9 +5664,11 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
case TARGET_NR_brk:
ret = do_brk(arg1);
break;
#ifdef TARGET_NR_fork
case TARGET_NR_fork:
ret = get_errno(do_fork(cpu_env, SIGCHLD, 0, 0, 0, 0));
break;
#endif
#ifdef TARGET_NR_waitpid
case TARGET_NR_waitpid:
{
@ -5699,6 +5703,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
break;
#endif
#ifdef TARGET_NR_link
case TARGET_NR_link:
{
void * p2;
@ -5712,6 +5717,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
#endif
#if defined(TARGET_NR_linkat)
case TARGET_NR_linkat:
{
@ -5729,12 +5735,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
break;
#endif
#ifdef TARGET_NR_unlink
case TARGET_NR_unlink:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(unlink(p));
unlock_user(p, arg1, 0);
break;
#endif
#if defined(TARGET_NR_unlinkat)
case TARGET_NR_unlinkat:
if (!(p = lock_user_string(arg2)))
@ -5851,12 +5859,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
break;
#endif
#ifdef TARGET_NR_mknod
case TARGET_NR_mknod:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(mknod(p, arg2, arg3));
unlock_user(p, arg1, 0);
break;
#endif
#if defined(TARGET_NR_mknodat)
case TARGET_NR_mknodat:
if (!(p = lock_user_string(arg2)))
@ -5865,12 +5875,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg2, 0);
break;
#endif
#ifdef TARGET_NR_chmod
case TARGET_NR_chmod:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(chmod(p, arg2));
unlock_user(p, arg1, 0);
break;
#endif
#ifdef TARGET_NR_break
case TARGET_NR_break:
goto unimplemented;
@ -6005,6 +6017,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
break;
#endif
#ifdef TARGET_NR_utimes
case TARGET_NR_utimes:
{
struct timeval *tvp, tv[2];
@ -6023,6 +6036,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
#endif
#if defined(TARGET_NR_futimesat)
case TARGET_NR_futimesat:
{
@ -6051,12 +6065,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
case TARGET_NR_gtty:
goto unimplemented;
#endif
#ifdef TARGET_NR_access
case TARGET_NR_access:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(access(path(p), arg2));
unlock_user(p, arg1, 0);
break;
#endif
#if defined(TARGET_NR_faccessat) && defined(__NR_faccessat)
case TARGET_NR_faccessat:
if (!(p = lock_user_string(arg2)))
@ -6081,6 +6097,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
case TARGET_NR_kill:
ret = get_errno(kill(arg1, target_to_host_signal(arg2)));
break;
#ifdef TARGET_NR_rename
case TARGET_NR_rename:
{
void *p2;
@ -6094,6 +6111,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
#endif
#if defined(TARGET_NR_renameat)
case TARGET_NR_renameat:
{
@ -6109,12 +6127,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
break;
#endif
#ifdef TARGET_NR_mkdir
case TARGET_NR_mkdir:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(mkdir(p, arg2));
unlock_user(p, arg1, 0);
break;
#endif
#if defined(TARGET_NR_mkdirat)
case TARGET_NR_mkdirat:
if (!(p = lock_user_string(arg2)))
@ -6123,18 +6143,22 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg2, 0);
break;
#endif
#ifdef TARGET_NR_rmdir
case TARGET_NR_rmdir:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(rmdir(p));
unlock_user(p, arg1, 0);
break;
#endif
case TARGET_NR_dup:
ret = get_errno(dup(arg1));
break;
#ifdef TARGET_NR_pipe
case TARGET_NR_pipe:
ret = do_pipe(cpu_env, arg1, 0, 0);
break;
#endif
#ifdef TARGET_NR_pipe2
case TARGET_NR_pipe2:
ret = do_pipe(cpu_env, arg1,
@ -6219,11 +6243,15 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = get_errno(chroot(p));
unlock_user(p, arg1, 0);
break;
#ifdef TARGET_NR_ustat
case TARGET_NR_ustat:
goto unimplemented;
#endif
#ifdef TARGET_NR_dup2
case TARGET_NR_dup2:
ret = get_errno(dup2(arg1, arg2));
break;
#endif
#if defined(CONFIG_DUP3) && defined(TARGET_NR_dup3)
case TARGET_NR_dup3:
ret = get_errno(dup3(arg1, arg2, arg3));
@ -6234,9 +6262,11 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = get_errno(getppid());
break;
#endif
#ifdef TARGET_NR_getpgrp
case TARGET_NR_getpgrp:
ret = get_errno(getpgrp());
break;
#endif
case TARGET_NR_setsid:
ret = get_errno(setsid());
break;
@ -6812,6 +6842,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
break;
#endif
#ifdef TARGET_NR_symlink
case TARGET_NR_symlink:
{
void *p2;
@ -6825,6 +6856,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
#endif
#if defined(TARGET_NR_symlinkat)
case TARGET_NR_symlinkat:
{
@ -6844,6 +6876,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
case TARGET_NR_oldlstat:
goto unimplemented;
#endif
#ifdef TARGET_NR_readlink
case TARGET_NR_readlink:
{
void *p2;
@ -6874,6 +6907,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
unlock_user(p, arg1, 0);
}
break;
#endif
#if defined(TARGET_NR_readlinkat)
case TARGET_NR_readlinkat:
{
@ -7273,22 +7307,28 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
}
break;
#ifdef TARGET_NR_stat
case TARGET_NR_stat:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(stat(path(p), &st));
unlock_user(p, arg1, 0);
goto do_stat;
#endif
#ifdef TARGET_NR_lstat
case TARGET_NR_lstat:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(lstat(path(p), &st));
unlock_user(p, arg1, 0);
goto do_stat;
#endif
case TARGET_NR_fstat:
{
ret = get_errno(fstat(arg1, &st));
#if defined(TARGET_NR_stat) || defined(TARGET_NR_lstat)
do_stat:
#endif
if (!is_error(ret)) {
struct target_stat *target_st;
@ -7576,6 +7616,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
break;
#endif
#ifdef TARGET_NR_getdents
case TARGET_NR_getdents:
#ifdef __NR_getdents
#if TARGET_ABI_BITS == 32 && HOST_LONG_BITS == 64
@ -7706,6 +7747,7 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
#endif
break;
#endif /* TARGET_NR_getdents */
#if defined(TARGET_NR_getdents64) && defined(__NR_getdents64)
case TARGET_NR_getdents64:
{
@ -7845,11 +7887,13 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = get_errno(fdatasync(arg1));
break;
#endif
#ifdef TARGET_NR__sysctl
case TARGET_NR__sysctl:
/* We don't implement this, but ENOTDIR is always a safe
return value. */
ret = -TARGET_ENOTDIR;
break;
#endif
case TARGET_NR_sched_getaffinity:
{
unsigned int mask_size;
@ -8296,12 +8340,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
ret = host_to_target_stat64(cpu_env, arg3, &st);
break;
#endif
#ifdef TARGET_NR_lchown
case TARGET_NR_lchown:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(lchown(p, low2highuid(arg2), low2highgid(arg3)));
unlock_user(p, arg1, 0);
break;
#endif
#ifdef TARGET_NR_getuid
case TARGET_NR_getuid:
ret = get_errno(high2lowuid(getuid()));
@ -8424,12 +8470,14 @@ abi_long do_syscall(void *cpu_env, int num, abi_long arg1,
}
break;
#endif
#ifdef TARGET_NR_chown
case TARGET_NR_chown:
if (!(p = lock_user_string(arg1)))
goto efault;
ret = get_errno(chown(p, low2highuid(arg2), low2highgid(arg3)));
unlock_user(p, arg1, 0);
break;
#endif
case TARGET_NR_setuid:
ret = get_errno(setuid(low2highuid(arg1)));
break;

14
linux-user/syscall_defs.h
View File

@ -64,8 +64,9 @@
#endif
#if defined(TARGET_I386) || defined(TARGET_ARM) || defined(TARGET_SH4) \
|| defined(TARGET_M68K) || defined(TARGET_CRIS) || defined(TARGET_UNICORE32) \
|| defined(TARGET_S390X) || defined(TARGET_OPENRISC)
|| defined(TARGET_M68K) || defined(TARGET_CRIS) \
|| defined(TARGET_UNICORE32) || defined(TARGET_S390X) \
|| defined(TARGET_OPENRISC) || defined(TARGET_TILEGX)
#define TARGET_IOC_SIZEBITS 14
#define TARGET_IOC_DIRBITS 2
@ -365,7 +366,8 @@ int do_sigaction(int sig, const struct target_sigaction *act,
|| defined(TARGET_PPC) || defined(TARGET_MIPS) || defined(TARGET_SH4) \
|| defined(TARGET_M68K) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) \
|| defined(TARGET_MICROBLAZE) || defined(TARGET_UNICORE32) \
|| defined(TARGET_S390X) || defined(TARGET_OPENRISC)
|| defined(TARGET_S390X) || defined(TARGET_OPENRISC) \
|| defined(TARGET_TILEGX)
#if defined(TARGET_SPARC)
#define TARGET_SA_NOCLDSTOP 8u
@ -1871,7 +1873,7 @@ struct target_stat {
abi_ulong target_st_ctime_nsec;
unsigned int __unused[2];
};
#elif defined(TARGET_OPENRISC)
#elif defined(TARGET_OPENRISC) || defined(TARGET_TILEGX)
/* These are the asm-generic versions of the stat and stat64 structures */
@ -2264,7 +2266,9 @@ struct target_flock {
struct target_flock64 {
short l_type;
short l_whence;
#if defined(TARGET_PPC) || defined(TARGET_X86_64) || defined(TARGET_MIPS) || defined(TARGET_SPARC) || defined(TARGET_HPPA) || defined (TARGET_MICROBLAZE)
#if defined(TARGET_PPC) || defined(TARGET_X86_64) || defined(TARGET_MIPS) \
|| defined(TARGET_SPARC) || defined(TARGET_HPPA) \
|| defined(TARGET_MICROBLAZE) || defined(TARGET_TILEGX)
int __pad;
#endif
unsigned long long l_start;

40
linux-user/tilegx/syscall.h Normal file
View File

@ -0,0 +1,40 @@
#ifndef TILEGX_SYSCALLS_H
#define TILEGX_SYSCALLS_H
#define UNAME_MACHINE "tilegx"
#define UNAME_MINIMUM_RELEASE "3.19"
#define MMAP_SHIFT TARGET_PAGE_BITS
#define TILEGX_IS_ERRNO(ret) \
((ret) > 0xfffffffffffff000ULL) /* errno is 0 -- 4096 */
typedef uint64_t tilegx_reg_t;
struct target_pt_regs {
union {
/* Saved main processor registers; 56..63 are special. */
tilegx_reg_t regs[56];
struct {
tilegx_reg_t __regs[53];
tilegx_reg_t tp; /* aliases regs[TREG_TP] */
tilegx_reg_t sp; /* aliases regs[TREG_SP] */
tilegx_reg_t lr; /* aliases regs[TREG_LR] */
};
};
/* Saved special registers. */
tilegx_reg_t pc; /* stored in EX_CONTEXT_K_0 */
tilegx_reg_t ex1; /* stored in EX_CONTEXT_K_1 (PL and ICS bit) */
tilegx_reg_t faultnum; /* fault number (INT_SWINT_1 for syscall) */
tilegx_reg_t orig_r0; /* r0 at syscall entry, else zero */
tilegx_reg_t flags; /* flags (see below) */
tilegx_reg_t cmpexch; /* value of CMPEXCH_VALUE SPR at interrupt */
tilegx_reg_t pad[2];
};
#define TARGET_MLOCKALL_MCL_CURRENT 1
#define TARGET_MLOCKALL_MCL_FUTURE 2
#endif

324
linux-user/tilegx/syscall_nr.h Normal file
View File

@ -0,0 +1,324 @@
#ifndef TILEGX_SYSCALL_NR
#define TILEGX_SYSCALL_NR
/*
* Copy from linux kernel asm-generic/unistd.h, which tilegx uses.
*/
#define TARGET_NR_io_setup 0
#define TARGET_NR_io_destroy 1
#define TARGET_NR_io_submit 2
#define TARGET_NR_io_cancel 3
#define TARGET_NR_io_getevents 4
#define TARGET_NR_setxattr 5
#define TARGET_NR_lsetxattr 6
#define TARGET_NR_fsetxattr 7
#define TARGET_NR_getxattr 8
#define TARGET_NR_lgetxattr 9
#define TARGET_NR_fgetxattr 10
#define TARGET_NR_listxattr 11
#define TARGET_NR_llistxattr 12
#define TARGET_NR_flistxattr 13
#define TARGET_NR_removexattr 14
#define TARGET_NR_lremovexattr 15
#define TARGET_NR_fremovexattr 16
#define TARGET_NR_getcwd 17
#define TARGET_NR_lookup_dcookie 18
#define TARGET_NR_eventfd2 19
#define TARGET_NR_epoll_create1 20
#define TARGET_NR_epoll_ctl 21
#define TARGET_NR_epoll_pwait 22
#define TARGET_NR_dup 23
#define TARGET_NR_dup3 24
#define TARGET_NR_fcntl 25
#define TARGET_NR_inotify_init1 26
#define TARGET_NR_inotify_add_watch 27
#define TARGET_NR_inotify_rm_watch 28
#define TARGET_NR_ioctl 29
#define TARGET_NR_ioprio_set 30
#define TARGET_NR_ioprio_get 31
#define TARGET_NR_flock 32
#define TARGET_NR_mknodat 33
#define TARGET_NR_mkdirat 34
#define TARGET_NR_unlinkat 35
#define TARGET_NR_symlinkat 36
#define TARGET_NR_linkat 37
#define TARGET_NR_renameat 38
#define TARGET_NR_umount2 39
#define TARGET_NR_mount 40
#define TARGET_NR_pivot_root 41
#define TARGET_NR_nfsservctl 42
#define TARGET_NR_statfs 43
#define TARGET_NR_fstatfs 44
#define TARGET_NR_truncate 45
#define TARGET_NR_ftruncate 46
#define TARGET_NR_fallocate 47
#define TARGET_NR_faccessat 48
#define TARGET_NR_chdir 49
#define TARGET_NR_fchdir 50
#define TARGET_NR_chroot 51
#define TARGET_NR_fchmod 52
#define TARGET_NR_fchmodat 53
#define TARGET_NR_fchownat 54
#define TARGET_NR_fchown 55
#define TARGET_NR_openat 56
#define TARGET_NR_close 57
#define TARGET_NR_vhangup 58
#define TARGET_NR_pipe2 59
#define TARGET_NR_quotactl 60
#define TARGET_NR_getdents64 61
#define TARGET_NR_lseek 62
#define TARGET_NR_read 63
#define TARGET_NR_write 64
#define TARGET_NR_readv 65
#define TARGET_NR_writev 66
#define TARGET_NR_pread64 67
#define TARGET_NR_pwrite64 68
#define TARGET_NR_preadv 69
#define TARGET_NR_pwritev 70
#define TARGET_NR_sendfile 71
#define TARGET_NR_pselect6 72
#define TARGET_NR_ppoll 73
#define TARGET_NR_signalfd4 74
#define TARGET_NR_vmsplice 75
#define TARGET_NR_splice 76
#define TARGET_NR_tee 77
#define TARGET_NR_readlinkat 78
#define TARGET_NR_fstatat64 79 /* let syscall.c known */
#define TARGET_NR_fstat 80
#define TARGET_NR_sync 81
#define TARGET_NR_fsync 82
#define TARGET_NR_fdatasync 83
#define TARGET_NR_sync_file_range 84 /* For tilegx, no range2 */
#define TARGET_NR_timerfd_create 85
#define TARGET_NR_timerfd_settime 86
#define TARGET_NR_timerfd_gettime 87
#define TARGET_NR_utimensat 88
#define TARGET_NR_acct 89
#define TARGET_NR_capget 90
#define TARGET_NR_capset 91
#define TARGET_NR_personality 92
#define TARGET_NR_exit 93
#define TARGET_NR_exit_group 94
#define TARGET_NR_waitid 95
#define TARGET_NR_set_tid_address 96
#define TARGET_NR_unshare 97
#define TARGET_NR_futex 98
#define TARGET_NR_set_robust_list 99
#define TARGET_NR_get_robust_list 100
#define TARGET_NR_nanosleep 101
#define TARGET_NR_getitimer 102
#define TARGET_NR_setitimer 103
#define TARGET_NR_kexec_load 104
#define TARGET_NR_init_module 105
#define TARGET_NR_delete_module 106
#define TARGET_NR_timer_create 107
#define TARGET_NR_timer_gettime 108
#define TARGET_NR_timer_getoverrun 109
#define TARGET_NR_timer_settime 110
#define TARGET_NR_timer_delete 111
#define TARGET_NR_clock_settime 112
#define TARGET_NR_clock_gettime 113
#define TARGET_NR_clock_getres 114
#define TARGET_NR_clock_nanosleep 115
#define TARGET_NR_syslog 116
#define TARGET_NR_ptrace 117
#define TARGET_NR_sched_setparam 118
#define TARGET_NR_sched_setscheduler 119
#define TARGET_NR_sched_getscheduler 120
#define TARGET_NR_sched_getparam 121
#define TARGET_NR_sched_setaffinity 122
#define TARGET_NR_sched_getaffinity 123
#define TARGET_NR_sched_yield 124
#define TARGET_NR_sched_get_priority_max 125
#define TARGET_NR_sched_get_priority_min 126
#define TARGET_NR_sched_rr_get_interval 127
#define TARGET_NR_restart_syscall 128
#define TARGET_NR_kill 129
#define TARGET_NR_tkill 130
#define TARGET_NR_tgkill 131
#define TARGET_NR_sigaltstack 132
#define TARGET_NR_rt_sigsuspend 133
#define TARGET_NR_rt_sigaction 134
#define TARGET_NR_rt_sigprocmask 135
#define TARGET_NR_rt_sigpending 136
#define TARGET_NR_rt_sigtimedwait 137
#define TARGET_NR_rt_sigqueueinfo 138
#define TARGET_NR_rt_sigreturn 139
#define TARGET_NR_setpriority 140
#define TARGET_NR_getpriority 141
#define TARGET_NR_reboot 142
#define TARGET_NR_setregid 143
#define TARGET_NR_setgid 144
#define TARGET_NR_setreuid 145
#define TARGET_NR_setuid 146
#define TARGET_NR_setresuid 147
#define TARGET_NR_getresuid 148
#define TARGET_NR_setresgid 149
#define TARGET_NR_getresgid 150
#define TARGET_NR_setfsuid 151
#define TARGET_NR_setfsgid 152
#define TARGET_NR_times 153
#define TARGET_NR_setpgid 154
#define TARGET_NR_getpgid 155
#define TARGET_NR_getsid 156
#define TARGET_NR_setsid 157
#define TARGET_NR_getgroups 158
#define TARGET_NR_setgroups 159
#define TARGET_NR_uname 160
#define TARGET_NR_sethostname 161
#define TARGET_NR_setdomainname 162
#define TARGET_NR_getrlimit 163
#define TARGET_NR_setrlimit 164
#define TARGET_NR_getrusage 165
#define TARGET_NR_umask 166
#define TARGET_NR_prctl 167
#define TARGET_NR_getcpu 168
#define TARGET_NR_gettimeofday 169
#define TARGET_NR_settimeofday 170
#define TARGET_NR_adjtimex 171
#define TARGET_NR_getpid 172
#define TARGET_NR_getppid 173
#define TARGET_NR_getuid 174
#define TARGET_NR_geteuid 175
#define TARGET_NR_getgid 176
#define TARGET_NR_getegid 177
#define TARGET_NR_gettid 178
#define TARGET_NR_sysinfo 179
#define TARGET_NR_mq_open 180
#define TARGET_NR_mq_unlink 181
#define TARGET_NR_mq_timedsend 182
#define TARGET_NR_mq_timedreceive 183
#define TARGET_NR_mq_notify 184
#define TARGET_NR_mq_getsetattr 185
#define TARGET_NR_msgget 186
#define TARGET_NR_msgctl 187
#define TARGET_NR_msgrcv 188
#define TARGET_NR_msgsnd 189
#define TARGET_NR_semget 190
#define TARGET_NR_semctl 191
#define TARGET_NR_semtimedop 192
#define TARGET_NR_semop 193
#define TARGET_NR_shmget 194
#define TARGET_NR_shmctl 195
#define TARGET_NR_shmat 196
#define TARGET_NR_shmdt 197
#define TARGET_NR_socket 198
#define TARGET_NR_socketpair 199
#define TARGET_NR_bind 200
#define TARGET_NR_listen 201
#define TARGET_NR_accept 202
#define TARGET_NR_connect 203
#define TARGET_NR_getsockname 204
#define TARGET_NR_getpeername 205
#define TARGET_NR_sendto 206
#define TARGET_NR_recvfrom 207
#define TARGET_NR_setsockopt 208
#define TARGET_NR_getsockopt 209
#define TARGET_NR_shutdown 210
#define TARGET_NR_sendmsg 211
#define TARGET_NR_recvmsg 212
#define TARGET_NR_readahead 213
#define TARGET_NR_brk 214
#define TARGET_NR_munmap 215
#define TARGET_NR_mremap 216
#define TARGET_NR_add_key 217
#define TARGET_NR_request_key 218
#define TARGET_NR_keyctl 219
#define TARGET_NR_clone 220
#define TARGET_NR_execve 221
#define TARGET_NR_mmap 222
#define TARGET_NR_fadvise64 223
#define TARGET_NR_swapon 224
#define TARGET_NR_swapoff 225
#define TARGET_NR_mprotect 226
#define TARGET_NR_msync 227
#define TARGET_NR_mlock 228
#define TARGET_NR_munlock 229
#define TARGET_NR_mlockall 230
#define TARGET_NR_munlockall 231
#define TARGET_NR_mincore 232
#define TARGET_NR_madvise 233
#define TARGET_NR_remap_file_pages 234
#define TARGET_NR_mbind 235
#define TARGET_NR_get_mempolicy 236
#define TARGET_NR_set_mempolicy 237
#define TARGET_NR_migrate_pages 238
#define TARGET_NR_move_pages 239
#define TARGET_NR_rt_tgsigqueueinfo 240
#define TARGET_NR_perf_event_open 241
#define TARGET_NR_accept4 242
#define TARGET_NR_recvmmsg 243
#define TARGET_NR_arch_specific_syscall 244
#define TARGET_NR_cacheflush 245 /* tilegx own syscall */
#define TARGET_NR_wait4 260
#define TARGET_NR_prlimit64 261
#define TARGET_NR_fanotify_init 262
#define TARGET_NR_fanotify_mark 263
#define TARGET_NR_name_to_handle_at 264
#define TARGET_NR_open_by_handle_at 265
#define TARGET_NR_clock_adjtime 266
#define TARGET_NR_syncfs 267
#define TARGET_NR_setns 268
#define TARGET_NR_sendmmsg 269
#define TARGET_NR_process_vm_readv 270
#define TARGET_NR_process_vm_writev 271
#define TARGET_NR_kcmp 272
#define TARGET_NR_finit_module 273
#define TARGET_NR_sched_setattr 274
#define TARGET_NR_sched_getattr 275
#define TARGET_NR_renameat2 276
#define TARGET_NR_seccomp 277
#define TARGET_NR_getrandom 278
#define TARGET_NR_memfd_create 279
#define TARGET_NR_bpf 280
#define TARGET_NR_execveat 281
#define TARGET_NR_open 1024
#define TARGET_NR_link 1025
#define TARGET_NR_unlink 1026
#define TARGET_NR_mknod 1027
#define TARGET_NR_chmod 1028
#define TARGET_NR_chown 1029
#define TARGET_NR_mkdir 1030
#define TARGET_NR_rmdir 1031
#define TARGET_NR_lchown 1032
#define TARGET_NR_access 1033
#define TARGET_NR_rename 1034
#define TARGET_NR_readlink 1035
#define TARGET_NR_symlink 1036
#define TARGET_NR_utimes 1037
#define TARGET_NR_stat64 1038 /* let syscall.c known */
#define TARGET_NR_lstat 1039
#define TARGET_NR_pipe 1040
#define TARGET_NR_dup2 1041
#define TARGET_NR_epoll_create 1042
#define TARGET_NR_inotify_init 1043
#define TARGET_NR_eventfd 1044
#define TARGET_NR_signalfd 1045
#define TARGET_NR_alarm 1059
#define TARGET_NR_getpgrp 1060
#define TARGET_NR_pause 1061
#define TARGET_NR_time 1062
#define TARGET_NR_utime 1063
#define TARGET_NR_creat 1064
#define TARGET_NR_getdents 1065
#define TARGET_NR_futimesat 1066
#define TARGET_NR_select 1067
#define TARGET_NR_poll 1068
#define TARGET_NR_epoll_wait 1069
#define TARGET_NR_ustat 1070
#define TARGET_NR_vfork 1071
#define TARGET_NR_oldwait4 1072
#define TARGET_NR_recv 1073
#define TARGET_NR_send 1074
#define TARGET_NR_bdflush 1075
#define TARGET_NR_umount 1076
#define TARGET_NR_uselib 1077
#define TARGET_NR__sysctl 1078
#define TARGET_NR_fork 1079
#endif

35
linux-user/tilegx/target_cpu.h Normal file
View File

@ -0,0 +1,35 @@
/*
* TILE-Gx specific CPU ABI and functions for linux-user
*
* Copyright (c) 2015 Chen Gang
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef TARGET_CPU_H
#define TARGET_CPU_H
static inline void cpu_clone_regs(CPUTLGState *env, target_ulong newsp)
{
if (newsp) {
env->regs[TILEGX_R_SP] = newsp;
}
env->regs[TILEGX_R_RE] = 0;
}
static inline void cpu_set_tls(CPUTLGState *env, target_ulong newtls)
{
env->regs[TILEGX_R_TP] = newtls;
}
#endif

28
linux-user/tilegx/target_signal.h Normal file
View File

@ -0,0 +1,28 @@
#ifndef TARGET_SIGNAL_H
#define TARGET_SIGNAL_H
#include "cpu.h"
/* this struct defines a stack used during syscall handling */
typedef struct target_sigaltstack {
abi_ulong ss_sp;
abi_int ss_flags;
abi_ulong ss_size;
} target_stack_t;
/*
* sigaltstack controls
*/
#define TARGET_SS_ONSTACK 1
#define TARGET_SS_DISABLE 2
#define TARGET_MINSIGSTKSZ 2048
#define TARGET_SIGSTKSZ 8192
static inline abi_ulong get_sp_from_cpustate(CPUTLGState *state)
{
return state->regs[TILEGX_R_SP];
}
#endif /* TARGET_SIGNAL_H */

46
linux-user/tilegx/target_structs.h Normal file
View File

@ -0,0 +1,46 @@
/*
* TILE-Gx specific structures for linux-user
*
* Copyright (c) 2015 Chen Gang
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef TARGET_STRUCTS_H
#define TARGET_STRUCTS_H
struct target_ipc_perm {
abi_int __key; /* Key. */
abi_uint uid; /* Owner's user ID. */
abi_uint gid; /* Owner's group ID. */
abi_uint cuid; /* Creator's user ID. */
abi_uint cgid; /* Creator's group ID. */
abi_uint mode; /* Read/write permission. */
abi_ushort __seq; /* Sequence number. */
};
struct target_shmid_ds {
struct target_ipc_perm shm_perm; /* operation permission struct */
abi_long shm_segsz; /* size of segment in bytes */
abi_ulong shm_atime; /* time of last shmat() */
abi_ulong shm_dtime; /* time of last shmdt() */
abi_ulong shm_ctime; /* time of last change by shmctl() */
abi_int shm_cpid; /* pid of creator */
abi_int shm_lpid; /* pid of last shmop */
abi_ushort shm_nattch; /* number of current attaches */
abi_ushort shm_unused; /* compatibility */
abi_ulong __unused4;
abi_ulong __unused5;
};
#endif

274
linux-user/tilegx/termbits.h Normal file
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@ -0,0 +1,274 @@
#ifndef TILEGX_TERMBITS_H
#define TILEGX_TERMBITS_H
/* From asm-generic/termbits.h, which is used by tilegx */
#define TARGET_NCCS 19
struct target_termios {
unsigned int c_iflag; /* input mode flags */
unsigned int c_oflag; /* output mode flags */
unsigned int c_cflag; /* control mode flags */
unsigned int c_lflag; /* local mode flags */
unsigned char c_line; /* line discipline */
unsigned char c_cc[TARGET_NCCS]; /* control characters */
};
struct target_termios2 {
unsigned int c_iflag; /* input mode flags */
unsigned int c_oflag; /* output mode flags */
unsigned int c_cflag; /* control mode flags */
unsigned int c_lflag; /* local mode flags */
unsigned char c_line; /* line discipline */
unsigned char c_cc[TARGET_NCCS]; /* control characters */
unsigned int c_ispeed; /* input speed */
unsigned int c_ospeed; /* output speed */
};
/* c_cc characters */
#define TARGET_VINTR 0
#define TARGET_VQUIT 1
#define TARGET_VERASE 2
#define TARGET_VKILL 3
#define TARGET_VEOF 4
#define TARGET_VTIME 5
#define TARGET_VMIN 6
#define TARGET_VSWTC 7
#define TARGET_VSTART 8
#define TARGET_VSTOP 9
#define TARGET_VSUSP 10
#define TARGET_VEOL 11
#define TARGET_VREPRINT 12
#define TARGET_VDISCARD 13
#define TARGET_VWERASE 14
#define TARGET_VLNEXT 15
#define TARGET_VEOL2 16
/* c_iflag bits */
#define TARGET_IGNBRK 0000001
#define TARGET_BRKINT 0000002
#define TARGET_IGNPAR 0000004
#define TARGET_PARMRK 0000010
#define TARGET_INPCK 0000020
#define TARGET_ISTRIP 0000040
#define TARGET_INLCR 0000100
#define TARGET_IGNCR 0000200
#define TARGET_ICRNL 0000400
#define TARGET_IUCLC 0001000
#define TARGET_IXON 0002000
#define TARGET_IXANY 0004000
#define TARGET_IXOFF 0010000
#define TARGET_IMAXBEL 0020000
#define TARGET_IUTF8 0040000
/* c_oflag bits */
#define TARGET_OPOST 0000001
#define TARGET_OLCUC 0000002
#define TARGET_ONLCR 0000004
#define TARGET_OCRNL 0000010
#define TARGET_ONOCR 0000020
#define TARGET_ONLRET 0000040
#define TARGET_OFILL 0000100
#define TARGET_OFDEL 0000200
#define TARGET_NLDLY 0000400
#define TARGET_NL0 0000000
#define TARGET_NL1 0000400
#define TARGET_CRDLY 0003000
#define TARGET_CR0 0000000
#define TARGET_CR1 0001000
#define TARGET_CR2 0002000
#define TARGET_CR3 0003000
#define TARGET_TABDLY 0014000
#define TARGET_TAB0 0000000
#define TARGET_TAB1 0004000
#define TARGET_TAB2 0010000
#define TARGET_TAB3 0014000
#define TARGET_XTABS 0014000
#define TARGET_BSDLY 0020000
#define TARGET_BS0 0000000
#define TARGET_BS1 0020000
#define TARGET_VTDLY 0040000
#define TARGET_VT0 0000000
#define TARGET_VT1 0040000
#define TARGET_FFDLY 0100000
#define TARGET_FF0 0000000
#define TARGET_FF1 0100000
/* c_cflag bit meaning */
#define TARGET_CBAUD 0010017
#define TARGET_B0 0000000 /* hang up */
#define TARGET_B50 0000001
#define TARGET_B75 0000002
#define TARGET_B110 0000003
#define TARGET_B134 0000004
#define TARGET_B150 0000005
#define TARGET_B200 0000006
#define TARGET_B300 0000007
#define TARGET_B600 0000010
#define TARGET_B1200 0000011
#define TARGET_B1800 0000012
#define TARGET_B2400 0000013
#define TARGET_B4800 0000014
#define TARGET_B9600 0000015
#define TARGET_B19200 0000016
#define TARGET_B38400 0000017
#define TARGET_EXTA TARGET_B19200
#define TARGET_EXTB TARGET_B38400
#define TARGET_CSIZE 0000060
#define TARGET_CS5 0000000
#define TARGET_CS6 0000020
#define TARGET_CS7 0000040
#define TARGET_CS8 0000060
#define TARGET_CSTOPB 0000100
#define TARGET_CREAD 0000200
#define TARGET_PARENB 0000400
#define TARGET_PARODD 0001000
#define TARGET_HUPCL 0002000
#define TARGET_CLOCAL 0004000
#define TARGET_CBAUDEX 0010000
#define TARGET_BOTHER 0010000
#define TARGET_B57600 0010001
#define TARGET_B115200 0010002
#define TARGET_B230400 0010003
#define TARGET_B460800 0010004
#define TARGET_B500000 0010005
#define TARGET_B576000 0010006
#define TARGET_B921600 0010007
#define TARGET_B1000000 0010010
#define TARGET_B1152000 0010011
#define TARGET_B1500000 0010012
#define TARGET_B2000000 0010013
#define TARGET_B2500000 0010014
#define TARGET_B3000000 0010015
#define TARGET_B3500000 0010016
#define TARGET_B4000000 0010017
#define TARGET_CIBAUD 002003600000 /* input baud rate */
#define TARGET_CMSPAR 010000000000 /* mark or space (stick) parity */
#define TARGET_CRTSCTS 020000000000 /* flow control */
#define TARGET_IBSHIFT 16 /* Shift from CBAUD to CIBAUD */
/* c_lflag bits */
#define TARGET_ISIG 0000001
#define TARGET_ICANON 0000002
#define TARGET_XCASE 0000004
#define TARGET_ECHO 0000010
#define TARGET_ECHOE 0000020
#define TARGET_ECHOK 0000040
#define TARGET_ECHONL 0000100
#define TARGET_NOFLSH 0000200
#define TARGET_TOSTOP 0000400
#define TARGET_ECHOCTL 0001000
#define TARGET_ECHOPRT 0002000
#define TARGET_ECHOKE 0004000
#define TARGET_FLUSHO 0010000
#define TARGET_PENDIN 0040000
#define TARGET_IEXTEN 0100000
#define TARGET_EXTPROC 0200000
/* tcflow() and TCXONC use these */
#define TARGET_TCOOFF 0
#define TARGET_TCOON 1
#define TARGET_TCIOFF 2
#define TARGET_TCION 3
/* tcflush() and TCFLSH use these */
#define TARGET_TCIFLUSH 0
#define TARGET_TCOFLUSH 1
#define TARGET_TCIOFLUSH 2
/* tcsetattr uses these */
#define TARGET_TCSANOW 0
#define TARGET_TCSADRAIN 1
#define TARGET_TCSAFLUSH 2
/* From asm-generic/ioctls.h, which is used by tilegx */
#define TARGET_TCGETS 0x5401
#define TARGET_TCSETS 0x5402
#define TARGET_TCSETSW 0x5403
#define TARGET_TCSETSF 0x5404
#define TARGET_TCGETA 0x5405
#define TARGET_TCSETA 0x5406
#define TARGET_TCSETAW 0x5407
#define TARGET_TCSETAF 0x5408
#define TARGET_TCSBRK 0x5409
#define TARGET_TCXONC 0x540A
#define TARGET_TCFLSH 0x540B
#define TARGET_TIOCEXCL 0x540C
#define TARGET_TIOCNXCL 0x540D
#define TARGET_TIOCSCTTY 0x540E
#define TARGET_TIOCGPGRP 0x540F
#define TARGET_TIOCSPGRP 0x5410
#define TARGET_TIOCOUTQ 0x5411
#define TARGET_TIOCSTI 0x5412
#define TARGET_TIOCGWINSZ 0x5413
#define TARGET_TIOCSWINSZ 0x5414
#define TARGET_TIOCMGET 0x5415
#define TARGET_TIOCMBIS 0x5416
#define TARGET_TIOCMBIC 0x5417
#define TARGET_TIOCMSET 0x5418
#define TARGET_TIOCGSOFTCAR 0x5419
#define TARGET_TIOCSSOFTCAR 0x541A
#define TARGET_FIONREAD 0x541B
#define TARGET_TIOCINQ TARGET_FIONREAD
#define TARGET_TIOCLINUX 0x541C
#define TARGET_TIOCCONS 0x541D
#define TARGET_TIOCGSERIAL 0x541E
#define TARGET_TIOCSSERIAL 0x541F
#define TARGET_TIOCPKT 0x5420
#define TARGET_FIONBIO 0x5421
#define TARGET_TIOCNOTTY 0x5422
#define TARGET_TIOCSETD 0x5423
#define TARGET_TIOCGETD 0x5424
#define TARGET_TCSBRKP 0x5425
#define TARGET_TIOCSBRK 0x5427
#define TARGET_TIOCCBRK 0x5428
#define TARGET_TIOCGSID 0x5429
#define TARGET_TCGETS2 TARGET_IOR('T', 0x2A, struct termios2)
#define TARGET_TCSETS2 TARGET_IOW('T', 0x2B, struct termios2)
#define TARGET_TCSETSW2 TARGET_IOW('T', 0x2C, struct termios2)
#define TARGET_TCSETSF2 TARGET_IOW('T', 0x2D, struct termios2)
#define TARGET_TIOCGRS485 0x542E
#define TARGET_TIOCSRS485 0x542F
#define TARGET_TIOCGPTN TARGET_IOR('T', 0x30, unsigned int)
#define TARGET_TIOCSPTLCK TARGET_IOW('T', 0x31, int)
#define TARGET_TIOCGDEV TARGET_IOR('T', 0x32, unsigned int)
#define TARGET_TCGETX 0x5432
#define TARGET_TCSETX 0x5433
#define TARGET_TCSETXF 0x5434
#define TARGET_TCSETXW 0x5435
#define TARGET_TIOCSIG TARGET_IOW('T', 0x36, int)
#define TARGET_TIOCVHANGUP 0x5437
#define TARGET_TIOCGPKT TARGET_IOR('T', 0x38, int)
#define TARGET_TIOCGPTLCK TARGET_IOR('T', 0x39, int)
#define TARGET_TIOCGEXCL TARGET_IOR('T', 0x40, int)
#define TARGET_FIONCLEX 0x5450
#define TARGET_FIOCLEX 0x5451
#define TARGET_FIOASYNC 0x5452
#define TARGET_TIOCSERCONFIG 0x5453
#define TARGET_TIOCSERGWILD 0x5454
#define TARGET_TIOCSERSWILD 0x5455
#define TARGET_TIOCGLCKTRMIOS 0x5456
#define TARGET_TIOCSLCKTRMIOS 0x5457
#define TARGET_TIOCSERGSTRUCT 0x5458
#define TARGET_TIOCSERGETLSR 0x5459
#define TARGET_TIOCSERGETMULTI 0x545A
#define TARGET_TIOCSERSETMULTI 0x545B
#define TARGET_TIOCMIWAIT 0x545C
#define TARGET_TIOCGICOUNT 0x545D
#define TARGET_FIOQSIZE 0x5460
#define TARGET_TIOCPKT_DATA 0
#define TARGET_TIOCPKT_FLUSHREAD 1
#define TARGET_TIOCPKT_FLUSHWRITE 2
#define TARGET_TIOCPKT_STOP 4
#define TARGET_TIOCPKT_START 8
#define TARGET_TIOCPKT_NOSTOP 16
#define TARGET_TIOCPKT_DOSTOP 32
#define TARGET_TIOCPKT_IOCTL 64
#define TARGET_TIOCSER_TEMT 0x01
#endif

15
target-arm/helper-a64.c
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@ -70,20 +70,7 @@ uint32_t HELPER(clz32)(uint32_t x)
uint64_t HELPER(rbit64)(uint64_t x)
{
/* assign the correct byte position */
x = bswap64(x);
/* assign the correct nibble position */
x = ((x & 0xf0f0f0f0f0f0f0f0ULL) >> 4)
| ((x & 0x0f0f0f0f0f0f0f0fULL) << 4);
/* assign the correct bit position */
x = ((x & 0x8888888888888888ULL) >> 3)
| ((x & 0x4444444444444444ULL) >> 1)
| ((x & 0x2222222222222222ULL) << 1)
| ((x & 0x1111111111111111ULL) << 3);
return x;
return revbit64(x);
}
/* Convert a softfloat float_relation_ (as returned by

12
target-arm/helper.c
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@ -5044,17 +5044,7 @@ uint32_t HELPER(udiv)(uint32_t num, uint32_t den)
uint32_t HELPER(rbit)(uint32_t x)
{
x = ((x & 0xff000000) >> 24)
| ((x & 0x00ff0000) >> 8)
| ((x & 0x0000ff00) << 8)
| ((x & 0x000000ff) << 24);
x = ((x & 0xf0f0f0f0) >> 4)
| ((x & 0x0f0f0f0f) << 4);
x = ((x & 0x88888888) >> 3)
| ((x & 0x44444444) >> 1)
| ((x & 0x22222222) << 1)
| ((x & 0x11111111) << 3);
return x;
return revbit32(x);
}
#if defined(CONFIG_USER_ONLY)

1
target-tilegx/Makefile.objs Normal file
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@ -0,0 +1 @@
obj-y += cpu.o translate.o helper.o simd_helper.o

173
target-tilegx/cpu.c Normal file
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@ -0,0 +1,173 @@
/*
* QEMU TILE-Gx CPU
*
* Copyright (c) 2015 Chen Gang
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see
* <http://www.gnu.org/licenses/lgpl-2.1.html>
*/
#include "cpu.h"
#include "qemu-common.h"
#include "hw/qdev-properties.h"
#include "migration/vmstate.h"
static void tilegx_cpu_dump_state(CPUState *cs, FILE *f,
fprintf_function cpu_fprintf, int flags)
{
static const char * const reg_names[TILEGX_R_COUNT] = {
"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
"r16", "r17", "r18", "r19", "r20", "r21", "r22", "r23",
"r24", "r25", "r26", "r27", "r28", "r29", "r30", "r31",
"r32", "r33", "r34", "r35", "r36", "r37", "r38", "r39",
"r40", "r41", "r42", "r43", "r44", "r45", "r46", "r47",
"r48", "r49", "r50", "r51", "bp", "tp", "sp", "lr"
};
TileGXCPU *cpu = TILEGX_CPU(cs);
CPUTLGState *env = &cpu->env;
int i;
for (i = 0; i < TILEGX_R_COUNT; i++) {
cpu_fprintf(f, "%-4s" TARGET_FMT_lx "%s",
reg_names[i], env->regs[i],
(i % 4) == 3 ? "\n" : " ");
}
cpu_fprintf(f, "PC " TARGET_FMT_lx " CEX " TARGET_FMT_lx "\n\n",
env->pc, env->spregs[TILEGX_SPR_CMPEXCH]);
}
TileGXCPU *cpu_tilegx_init(const char *cpu_model)
{
TileGXCPU *cpu;
cpu = TILEGX_CPU(object_new(TYPE_TILEGX_CPU));
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
return cpu;
}
static void tilegx_cpu_set_pc(CPUState *cs, vaddr value)
{
TileGXCPU *cpu = TILEGX_CPU(cs);
cpu->env.pc = value;
}
static bool tilegx_cpu_has_work(CPUState *cs)
{
return true;
}
static void tilegx_cpu_reset(CPUState *s)
{
TileGXCPU *cpu = TILEGX_CPU(s);
TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(cpu);
CPUTLGState *env = &cpu->env;
tcc->parent_reset(s);
memset(env, 0, sizeof(CPUTLGState));
tlb_flush(s, 1);
}
static void tilegx_cpu_realizefn(DeviceState *dev, Error **errp)
{
CPUState *cs = CPU(dev);
TileGXCPUClass *tcc = TILEGX_CPU_GET_CLASS(dev);
cpu_reset(cs);
qemu_init_vcpu(cs);
tcc->parent_realize(dev, errp);
}
static void tilegx_cpu_initfn(Object *obj)
{
CPUState *cs = CPU(obj);
TileGXCPU *cpu = TILEGX_CPU(obj);
CPUTLGState *env = &cpu->env;
static bool tcg_initialized;
cs->env_ptr = env;
cpu_exec_init(cs, &error_abort);
if (tcg_enabled() && !tcg_initialized) {
tcg_initialized = true;
tilegx_tcg_init();
}
}
static void tilegx_cpu_do_interrupt(CPUState *cs)
{
cs->exception_index = -1;
}
static int tilegx_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int mmu_idx)
{
TileGXCPU *cpu = TILEGX_CPU(cs);
cs->exception_index = TILEGX_EXCP_SEGV;
cpu->env.excaddr = address;
return 1;
}
static bool tilegx_cpu_exec_interrupt(CPUState *cs, int interrupt_request)
{
if (interrupt_request & CPU_INTERRUPT_HARD) {
tilegx_cpu_do_interrupt(cs);
return true;
}
return false;
}
static void tilegx_cpu_class_init(ObjectClass *oc, void *data)
{
DeviceClass *dc = DEVICE_CLASS(oc);
CPUClass *cc = CPU_CLASS(oc);
TileGXCPUClass *tcc = TILEGX_CPU_CLASS(oc);
tcc->parent_realize = dc->realize;
dc->realize = tilegx_cpu_realizefn;
tcc->parent_reset = cc->reset;
cc->reset = tilegx_cpu_reset;
cc->has_work = tilegx_cpu_has_work;
cc->do_interrupt = tilegx_cpu_do_interrupt;
cc->cpu_exec_interrupt = tilegx_cpu_exec_interrupt;
cc->dump_state = tilegx_cpu_dump_state;
cc->set_pc = tilegx_cpu_set_pc;
cc->handle_mmu_fault = tilegx_cpu_handle_mmu_fault;
cc->gdb_num_core_regs = 0;
}
static const TypeInfo tilegx_cpu_type_info = {
.name = TYPE_TILEGX_CPU,
.parent = TYPE_CPU,
.instance_size = sizeof(TileGXCPU),
.instance_init = tilegx_cpu_initfn,
.class_size = sizeof(TileGXCPUClass),
.class_init = tilegx_cpu_class_init,
};
static void tilegx_cpu_register_types(void)
{
type_register_static(&tilegx_cpu_type_info);
}
type_init(tilegx_cpu_register_types)

179
target-tilegx/cpu.h Normal file
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@ -0,0 +1,179 @@
/*
* TILE-Gx virtual CPU header
*
* Copyright (c) 2015 Chen Gang
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
*/
#ifndef CPU_TILEGX_H
#define CPU_TILEGX_H
#include "config.h"
#include "qemu-common.h"
#define TARGET_LONG_BITS 64
#define CPUArchState struct CPUTLGState
#include "exec/cpu-defs.h"
/* TILE-Gx common register alias */
#define TILEGX_R_RE 0 /* 0 register, for function/syscall return value */
#define TILEGX_R_ERR 1 /* 1 register, for syscall errno flag */
#define TILEGX_R_NR 10 /* 10 register, for syscall number */
#define TILEGX_R_BP 52 /* 52 register, optional frame pointer */
#define TILEGX_R_TP 53 /* TP register, thread local storage data */
#define TILEGX_R_SP 54 /* SP register, stack pointer */
#define TILEGX_R_LR 55 /* LR register, may save pc, but it is not pc */
#define TILEGX_R_COUNT 56 /* Only 56 registers are really useful */
#define TILEGX_R_SN 56 /* SN register, obsoleted, it likes zero register */
#define TILEGX_R_IDN0 57 /* IDN0 register, cause IDN_ACCESS exception */
#define TILEGX_R_IDN1 58 /* IDN1 register, cause IDN_ACCESS exception */
#define TILEGX_R_UDN0 59 /* UDN0 register, cause UDN_ACCESS exception */
#define TILEGX_R_UDN1 60 /* UDN1 register, cause UDN_ACCESS exception */
#define TILEGX_R_UDN2 61 /* UDN2 register, cause UDN_ACCESS exception */
#define TILEGX_R_UDN3 62 /* UDN3 register, cause UDN_ACCESS exception */
#define TILEGX_R_ZERO 63 /* Zero register, always zero */
#define TILEGX_R_NOREG 255 /* Invalid register value */
/* TILE-Gx special registers used by outside */
enum {
TILEGX_SPR_CMPEXCH = 0,
TILEGX_SPR_CRITICAL_SEC = 1,
TILEGX_SPR_SIM_CONTROL = 2,
TILEGX_SPR_COUNT
};
/* Exception numbers */
typedef enum {
TILEGX_EXCP_NONE = 0,
TILEGX_EXCP_SYSCALL = 1,
TILEGX_EXCP_SEGV = 2,
TILEGX_EXCP_OPCODE_UNKNOWN = 0x101,
TILEGX_EXCP_OPCODE_UNIMPLEMENTED = 0x102,
TILEGX_EXCP_OPCODE_CMPEXCH = 0x103,
TILEGX_EXCP_OPCODE_CMPEXCH4 = 0x104,
TILEGX_EXCP_OPCODE_EXCH = 0x105,
TILEGX_EXCP_OPCODE_EXCH4 = 0x106,
TILEGX_EXCP_OPCODE_FETCHADD = 0x107,
TILEGX_EXCP_OPCODE_FETCHADD4 = 0x108,
TILEGX_EXCP_OPCODE_FETCHADDGEZ = 0x109,
TILEGX_EXCP_OPCODE_FETCHADDGEZ4 = 0x10a,
TILEGX_EXCP_OPCODE_FETCHAND = 0x10b,
TILEGX_EXCP_OPCODE_FETCHAND4 = 0x10c,
TILEGX_EXCP_OPCODE_FETCHOR = 0x10d,
TILEGX_EXCP_OPCODE_FETCHOR4 = 0x10e,
TILEGX_EXCP_REG_IDN_ACCESS = 0x181,
TILEGX_EXCP_REG_UDN_ACCESS = 0x182,
TILEGX_EXCP_UNALIGNMENT = 0x201,
TILEGX_EXCP_DBUG_BREAK = 0x301
} TileExcp;
typedef struct CPUTLGState {
uint64_t regs[TILEGX_R_COUNT]; /* Common used registers by outside */
uint64_t spregs[TILEGX_SPR_COUNT]; /* Special used registers by outside */
uint64_t pc; /* Current pc */
#if defined(CONFIG_USER_ONLY)
uint64_t atomic_srca; /* Arguments to atomic "exceptions" */
uint64_t atomic_srcb;
uint32_t atomic_dstr;
uint64_t excaddr; /* exception address */
#endif
CPU_COMMON
} CPUTLGState;
#include "qom/cpu.h"
#define TYPE_TILEGX_CPU "tilegx-cpu"
#define TILEGX_CPU_CLASS(klass) \
OBJECT_CLASS_CHECK(TileGXCPUClass, (klass), TYPE_TILEGX_CPU)
#define TILEGX_CPU(obj) \
OBJECT_CHECK(TileGXCPU, (obj), TYPE_TILEGX_CPU)
#define TILEGX_CPU_GET_CLASS(obj) \
OBJECT_GET_CLASS(TileGXCPUClass, (obj), TYPE_TILEGX_CPU)
/**
* TileGXCPUClass:
* @parent_realize: The parent class' realize handler.
* @parent_reset: The parent class' reset handler.
*
* A Tile-Gx CPU model.
*/
typedef struct TileGXCPUClass {
/*< private >*/
CPUClass parent_class;
/*< public >*/
DeviceRealize parent_realize;
void (*parent_reset)(CPUState *cpu);
} TileGXCPUClass;
/**
* TileGXCPU:
* @env: #CPUTLGState
*
* A Tile-GX CPU.
*/
typedef struct TileGXCPU {
/*< private >*/
CPUState parent_obj;
/*< public >*/
CPUTLGState env;
} TileGXCPU;
static inline TileGXCPU *tilegx_env_get_cpu(CPUTLGState *env)
{
return container_of(env, TileGXCPU, env);
}
#define ENV_GET_CPU(e) CPU(tilegx_env_get_cpu(e))
#define ENV_OFFSET offsetof(TileGXCPU, env)
/* TILE-Gx memory attributes */
#define TARGET_PAGE_BITS 16 /* TILE-Gx uses 64KB page size */
#define TARGET_PHYS_ADDR_SPACE_BITS 42
#define TARGET_VIRT_ADDR_SPACE_BITS 64
#define MMU_USER_IDX 0 /* Current memory operation is in user mode */
#include "exec/cpu-all.h"
void tilegx_tcg_init(void);
int cpu_tilegx_exec(CPUState *s);
int cpu_tilegx_signal_handler(int host_signum, void *pinfo, void *puc);
TileGXCPU *cpu_tilegx_init(const char *cpu_model);
#define cpu_init(cpu_model) CPU(cpu_tilegx_init(cpu_model))
#define cpu_exec cpu_tilegx_exec
#define cpu_gen_code cpu_tilegx_gen_code
#define cpu_signal_handler cpu_tilegx_signal_handler
static inline void cpu_get_tb_cpu_state(CPUTLGState *env, target_ulong *pc,
target_ulong *cs_base, int *flags)
{
*pc = env->pc;
*cs_base = 0;
*flags = 0;
}
#include "exec/exec-all.h"
#endif

80
target-tilegx/helper.c Normal file
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@ -0,0 +1,80 @@
/*
* QEMU TILE-Gx helpers
*
* Copyright (c) 2015 Chen Gang
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see
* <http://www.gnu.org/licenses/lgpl-2.1.html>
*/
#include "cpu.h"
#include "qemu-common.h"
#include "exec/helper-proto.h"
void helper_exception(CPUTLGState *env, uint32_t excp)
{
CPUState *cs = CPU(tilegx_env_get_cpu(env));
cs->exception_index = excp;
cpu_loop_exit(cs);
}
uint64_t helper_cntlz(uint64_t arg)
{
return clz64(arg);
}
uint64_t helper_cnttz(uint64_t arg)
{
return ctz64(arg);
}
uint64_t helper_pcnt(uint64_t arg)
{
return ctpop64(arg);
}
uint64_t helper_revbits(uint64_t arg)
{
return revbit64(arg);
}
/*
* Functional Description
* uint64_t a = rf[SrcA];
* uint64_t b = rf[SrcB];
* uint64_t d = rf[Dest];
* uint64_t output = 0;
* unsigned int counter;
* for (counter = 0; counter < (WORD_SIZE / BYTE_SIZE); counter++)
* {
* int sel = getByte (b, counter) & 0xf;
* uint8_t byte = (sel < 8) ? getByte (d, sel) : getByte (a, (sel - 8));
* output = setByte (output, counter, byte);
* }
* rf[Dest] = output;
*/
uint64_t helper_shufflebytes(uint64_t dest, uint64_t srca, uint64_t srcb)
{
uint64_t vdst = 0;
int count;
for (count = 0; count < 64; count += 8) {
uint64_t sel = srcb >> count;
uint64_t src = (sel & 8) ? srca : dest;
vdst |= extract64(src, (sel & 7) * 8, 8) << count;
}
return vdst;
}

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DEF_HELPER_2(exception, noreturn, env, i32)
DEF_HELPER_FLAGS_1(cntlz, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(cnttz, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(pcnt, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_1(revbits, TCG_CALL_NO_RWG_SE, i64, i64)
DEF_HELPER_FLAGS_3(shufflebytes, TCG_CALL_NO_RWG_SE, i64, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shl, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shru, TCG_CALL_NO_RWG_SE, i64, i64, i64)
DEF_HELPER_FLAGS_2(v1shrs, TCG_CALL_NO_RWG_SE, i64, i64, i64)

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/*
* QEMU TILE-Gx helpers
*
* Copyright (c) 2015 Chen Gang
*
* This library is free software; you can redistribute it and/or
* modify it under the terms of the GNU Lesser General Public
* License as published by the Free Software Foundation; either
* version 2.1 of the License, or (at your option) any later version.
*
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see
* <http://www.gnu.org/licenses/lgpl-2.1.html>
*/
#include "cpu.h"
#include "qemu-common.h"
#include "exec/helper-proto.h"
uint64_t helper_v1shl(uint64_t a, uint64_t b)
{
uint64_t m;
b &= 7;
m = 0x0101010101010101ULL * (0xff >> b);
return (a & m) << b;
}
uint64_t helper_v1shru(uint64_t a, uint64_t b)
{
uint64_t m;
b &= 7;
m = 0x0101010101010101ULL * ((0xff << b) & 0xff);
return (a & m) >> b;
}
uint64_t helper_v1shrs(uint64_t a, uint64_t b)
{
uint64_t r = 0;
int i;
b &= 7;
for (i = 0; i < 64; i += 8) {
int64_t ae = (int8_t)(a >> i);
r |= ((ae >> b) & 0xff) << i;
}
return r;
}

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/*
* Copyright 2011 Tilera Corporation. All Rights Reserved.
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation, version 2.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
* NON INFRINGEMENT. See the GNU General Public License for
* more details.
*/
#ifndef __DOXYGEN__
#ifndef __ARCH_SPR_DEF_64_H__
#define __ARCH_SPR_DEF_64_H__
#define SPR_AUX_PERF_COUNT_0 0x2105
#define SPR_AUX_PERF_COUNT_1 0x2106
#define SPR_AUX_PERF_COUNT_CTL 0x2107
#define SPR_AUX_PERF_COUNT_STS 0x2108
#define SPR_CMPEXCH_VALUE 0x2780
#define SPR_CYCLE 0x2781
#define SPR_DONE 0x2705
#define SPR_DSTREAM_PF 0x2706
#define SPR_EVENT_BEGIN 0x2782
#define SPR_EVENT_END 0x2783
#define SPR_EX_CONTEXT_0_0 0x2580
#define SPR_EX_CONTEXT_0_1 0x2581
#define SPR_EX_CONTEXT_0_1__PL_SHIFT 0
#define SPR_EX_CONTEXT_0_1__PL_RMASK 0x3
#define SPR_EX_CONTEXT_0_1__PL_MASK 0x3
#define SPR_EX_CONTEXT_0_1__ICS_SHIFT 2
#define SPR_EX_CONTEXT_0_1__ICS_RMASK 0x1
#define SPR_EX_CONTEXT_0_1__ICS_MASK 0x4
#define SPR_EX_CONTEXT_1_0 0x2480
#define SPR_EX_CONTEXT_1_1 0x2481
#define SPR_EX_CONTEXT_1_1__PL_SHIFT 0
#define SPR_EX_CONTEXT_1_1__PL_RMASK 0x3
#define SPR_EX_CONTEXT_1_1__PL_MASK 0x3
#define SPR_EX_CONTEXT_1_1__ICS_SHIFT 2
#define SPR_EX_CONTEXT_1_1__ICS_RMASK 0x1
#define SPR_EX_CONTEXT_1_1__ICS_MASK 0x4
#define SPR_EX_CONTEXT_2_0 0x2380
#define SPR_EX_CONTEXT_2_1 0x2381
#define SPR_EX_CONTEXT_2_1__PL_SHIFT 0
#define SPR_EX_CONTEXT_2_1__PL_RMASK 0x3
#define SPR_EX_CONTEXT_2_1__PL_MASK 0x3
#define SPR_EX_CONTEXT_2_1__ICS_SHIFT 2
#define SPR_EX_CONTEXT_2_1__ICS_RMASK 0x1
#define SPR_EX_CONTEXT_2_1__ICS_MASK 0x4
#define SPR_FAIL 0x2707
#define SPR_IDN_AVAIL_EN 0x1a05
#define SPR_IDN_DATA_AVAIL 0x0a80
#define SPR_IDN_DEADLOCK_TIMEOUT 0x1806
#define SPR_IDN_DEMUX_COUNT_0 0x0a05
#define SPR_IDN_DEMUX_COUNT_1 0x0a06
#define SPR_IDN_DIRECTION_PROTECT 0x1405
#define SPR_IDN_PENDING 0x0a08
#define SPR_ILL_TRANS_REASON__I_STREAM_VA_RMASK 0x1
#define SPR_INTCTRL_0_STATUS 0x2505
#define SPR_INTCTRL_1_STATUS 0x2405
#define SPR_INTCTRL_2_STATUS 0x2305
#define SPR_INTERRUPT_CRITICAL_SECTION 0x2708
#define SPR_INTERRUPT_MASK_0 0x2506
#define SPR_INTERRUPT_MASK_1 0x2406
#define SPR_INTERRUPT_MASK_2 0x2306
#define SPR_INTERRUPT_MASK_RESET_0 0x2507
#define SPR_INTERRUPT_MASK_RESET_1 0x2407
#define SPR_INTERRUPT_MASK_RESET_2 0x2307
#define SPR_INTERRUPT_MASK_SET_0 0x2508
#define SPR_INTERRUPT_MASK_SET_1 0x2408
#define SPR_INTERRUPT_MASK_SET_2 0x2308
#define SPR_INTERRUPT_VECTOR_BASE_0 0x2509
#define SPR_INTERRUPT_VECTOR_BASE_1 0x2409
#define SPR_INTERRUPT_VECTOR_BASE_2 0x2309
#define SPR_INTERRUPT_VECTOR_BASE_3 0x2209
#define SPR_IPI_EVENT_0 0x1f05
#define SPR_IPI_EVENT_1 0x1e05
#define SPR_IPI_EVENT_2 0x1d05
#define SPR_IPI_EVENT_RESET_0 0x1f06
#define SPR_IPI_EVENT_RESET_1 0x1e06
#define SPR_IPI_EVENT_RESET_2 0x1d06
#define SPR_IPI_EVENT_SET_0 0x1f07
#define SPR_IPI_EVENT_SET_1 0x1e07
#define SPR_IPI_EVENT_SET_2 0x1d07
#define SPR_IPI_MASK_0 0x1f08
#define SPR_IPI_MASK_1 0x1e08
#define SPR_IPI_MASK_2 0x1d08
#define SPR_IPI_MASK_RESET_0 0x1f09
#define SPR_IPI_MASK_RESET_1 0x1e09
#define SPR_IPI_MASK_RESET_2 0x1d09
#define SPR_IPI_MASK_SET_0 0x1f0a
#define SPR_IPI_MASK_SET_1 0x1e0a
#define SPR_IPI_MASK_SET_2 0x1d0a
#define SPR_MPL_AUX_PERF_COUNT_SET_0 0x2100
#define SPR_MPL_AUX_PERF_COUNT_SET_1 0x2101
#define SPR_MPL_AUX_PERF_COUNT_SET_2 0x2102
#define SPR_MPL_AUX_TILE_TIMER_SET_0 0x1700
#define SPR_MPL_AUX_TILE_TIMER_SET_1 0x1701
#define SPR_MPL_AUX_TILE_TIMER_SET_2 0x1702
#define SPR_MPL_IDN_ACCESS_SET_0 0x0a00
#define SPR_MPL_IDN_ACCESS_SET_1 0x0a01
#define SPR_MPL_IDN_ACCESS_SET_2 0x0a02
#define SPR_MPL_IDN_AVAIL_SET_0 0x1a00
#define SPR_MPL_IDN_AVAIL_SET_1 0x1a01
#define SPR_MPL_IDN_AVAIL_SET_2 0x1a02
#define SPR_MPL_IDN_COMPLETE_SET_0 0x0500
#define SPR_MPL_IDN_COMPLETE_SET_1 0x0501
#define SPR_MPL_IDN_COMPLETE_SET_2 0x0502
#define SPR_MPL_IDN_FIREWALL_SET_0 0x1400
#define SPR_MPL_IDN_FIREWALL_SET_1 0x1401
#define SPR_MPL_IDN_FIREWALL_SET_2 0x1402
#define SPR_MPL_IDN_TIMER_SET_0 0x1800
#define SPR_MPL_IDN_TIMER_SET_1 0x1801
#define SPR_MPL_IDN_TIMER_SET_2 0x1802
#define SPR_MPL_INTCTRL_0_SET_0 0x2500
#define SPR_MPL_INTCTRL_0_SET_1 0x2501
#define SPR_MPL_INTCTRL_0_SET_2 0x2502
#define SPR_MPL_INTCTRL_1_SET_0 0x2400
#define SPR_MPL_INTCTRL_1_SET_1 0x2401
#define SPR_MPL_INTCTRL_1_SET_2 0x2402
#define SPR_MPL_INTCTRL_2_SET_0 0x2300
#define SPR_MPL_INTCTRL_2_SET_1 0x2301
#define SPR_MPL_INTCTRL_2_SET_2 0x2302
#define SPR_MPL_IPI_0 0x1f04
#define SPR_MPL_IPI_0_SET_0 0x1f00
#define SPR_MPL_IPI_0_SET_1 0x1f01
#define SPR_MPL_IPI_0_SET_2 0x1f02
#define SPR_MPL_IPI_1 0x1e04
#define SPR_MPL_IPI_1_SET_0 0x1e00
#define SPR_MPL_IPI_1_SET_1 0x1e01
#define SPR_MPL_IPI_1_SET_2 0x1e02
#define SPR_MPL_IPI_2 0x1d04
#define SPR_MPL_IPI_2_SET_0 0x1d00
#define SPR_MPL_IPI_2_SET_1 0x1d01
#define SPR_MPL_IPI_2_SET_2 0x1d02
#define SPR_MPL_PERF_COUNT_SET_0 0x2000
#define SPR_MPL_PERF_COUNT_SET_1 0x2001
#define SPR_MPL_PERF_COUNT_SET_2 0x2002
#define SPR_MPL_UDN_ACCESS_SET_0 0x0b00
#define SPR_MPL_UDN_ACCESS_SET_1 0x0b01
#define SPR_MPL_UDN_ACCESS_SET_2 0x0b02
#define SPR_MPL_UDN_AVAIL_SET_0 0x1b00
#define SPR_MPL_UDN_AVAIL_SET_1 0x1b01
#define SPR_MPL_UDN_AVAIL_SET_2 0x1b02
#define SPR_MPL_UDN_COMPLETE_SET_0 0x0600
#define SPR_MPL_UDN_COMPLETE_SET_1 0x0601
#define SPR_MPL_UDN_COMPLETE_SET_2 0x0602
#define SPR_MPL_UDN_FIREWALL_SET_0 0x1500
#define SPR_MPL_UDN_FIREWALL_SET_1 0x1501
#define SPR_MPL_UDN_FIREWALL_SET_2 0x1502
#define SPR_MPL_UDN_TIMER_SET_0 0x1900
#define SPR_MPL_UDN_TIMER_SET_1 0x1901
#define SPR_MPL_UDN_TIMER_SET_2 0x1902
#define SPR_MPL_WORLD_ACCESS_SET_0 0x2700
#define SPR_MPL_WORLD_ACCESS_SET_1 0x2701
#define SPR_MPL_WORLD_ACCESS_SET_2 0x2702
#define SPR_PASS 0x2709
#define SPR_PERF_COUNT_0 0x2005
#define SPR_PERF_COUNT_1 0x2006
#define SPR_PERF_COUNT_CTL 0x2007
#define SPR_PERF_COUNT_DN_CTL 0x2008
#define SPR_PERF_COUNT_STS 0x2009
#define SPR_PROC_STATUS 0x2784
#define SPR_SIM_CONTROL 0x2785
#define SPR_SINGLE_STEP_CONTROL_0 0x0405
#define SPR_SINGLE_STEP_CONTROL_0__CANCELED_MASK 0x1
#define SPR_SINGLE_STEP_CONTROL_0__INHIBIT_MASK 0x2
#define SPR_SINGLE_STEP_CONTROL_1 0x0305
#define SPR_SINGLE_STEP_CONTROL_1__CANCELED_MASK 0x1
#define SPR_SINGLE_STEP_CONTROL_1__INHIBIT_MASK 0x2
#define SPR_SINGLE_STEP_CONTROL_2 0x0205
#define SPR_SINGLE_STEP_CONTROL_2__CANCELED_MASK 0x1
#define SPR_SINGLE_STEP_CONTROL_2__INHIBIT_MASK 0x2
#define SPR_SINGLE_STEP_EN_0_0 0x250a
#define SPR_SINGLE_STEP_EN_0_1 0x240a
#define SPR_SINGLE_STEP_EN_0_2 0x230a
#define SPR_SINGLE_STEP_EN_1_0 0x250b
#define SPR_SINGLE_STEP_EN_1_1 0x240b
#define SPR_SINGLE_STEP_EN_1_2 0x230b
#define SPR_SINGLE_STEP_EN_2_0 0x250c
#define SPR_SINGLE_STEP_EN_2_1 0x240c
#define SPR_SINGLE_STEP_EN_2_2 0x230c
#define SPR_SYSTEM_SAVE_0_0 0x2582
#define SPR_SYSTEM_SAVE_0_1 0x2583
#define SPR_SYSTEM_SAVE_0_2 0x2584
#define SPR_SYSTEM_SAVE_0_3 0x2585
#define SPR_SYSTEM_SAVE_1_0 0x2482
#define SPR_SYSTEM_SAVE_1_1 0x2483
#define SPR_SYSTEM_SAVE_1_2 0x2484
#define SPR_SYSTEM_SAVE_1_3 0x2485
#define SPR_SYSTEM_SAVE_2_0 0x2382
#define SPR_SYSTEM_SAVE_2_1 0x2383
#define SPR_SYSTEM_SAVE_2_2 0x2384
#define SPR_SYSTEM_SAVE_2_3 0x2385
#define SPR_TILE_COORD 0x270b
#define SPR_TILE_RTF_HWM 0x270c
#define SPR_TILE_TIMER_CONTROL 0x1605
#define SPR_UDN_AVAIL_EN 0x1b05
#define SPR_UDN_DATA_AVAIL 0x0b80
#define SPR_UDN_DEADLOCK_TIMEOUT 0x1906
#define SPR_UDN_DEMUX_COUNT_0 0x0b05
#define SPR_UDN_DEMUX_COUNT_1 0x0b06
#define SPR_UDN_DEMUX_COUNT_2 0x0b07
#define SPR_UDN_DEMUX_COUNT_3 0x0b08
#define SPR_UDN_DIRECTION_PROTECT 0x1505
#define SPR_UDN_PENDING 0x0b0a
#define SPR_WATCH_MASK 0x200a
#define SPR_WATCH_VAL 0x200b
#endif /* !defined(__ARCH_SPR_DEF_64_H__) */
#endif /* !defined(__DOXYGEN__) */

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