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target/s390x: Handle tec in s390_cpu_tlb_fill 

As a step toward moving all excption handling out of mmu_translate,
copy handling of the LowCore tec value from trigger_access_exception
into s390_cpu_tlb_fill.  So far this new plumbing isn't used.

Reviewed-by: David Hildenbrand <david@redhat.com>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20191001171614.8405-7-richard.henderson@linaro.org>
Signed-off-by: David Hildenbrand <david@redhat.com>
This commit is contained in:
Richard Henderson 2019-10-01 10:16:02 -07:00 committed by David Hildenbrand
parent 18ab936d00
commit 1ab3302886
1 changed files with 6 additions and 1 deletions
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7
target/s390x/excp_helper.c
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@ -126,7 +126,7 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
S390CPU *cpu = S390_CPU(cs); S390CPU *cpu = S390_CPU(cs);
CPUS390XState *env = &cpu->env; CPUS390XState *env = &cpu->env;
target_ulong vaddr, raddr; target_ulong vaddr, raddr;
uint64_t asc; uint64_t asc, tec;
int prot, fail, excp; int prot, fail, excp;
qemu_log_mask(CPU_LOG_MMU, "%s: addr 0x%" VADDR_PRIx " rw %d mmu_idx %d\n", qemu_log_mask(CPU_LOG_MMU, "%s: addr 0x%" VADDR_PRIx " rw %d mmu_idx %d\n",
@ -162,6 +162,7 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
"%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n", "%s: raddr %" PRIx64 " > ram_size %" PRIx64 "\n",
__func__, (uint64_t)raddr, (uint64_t)ram_size); __func__, (uint64_t)raddr, (uint64_t)ram_size);
excp = PGM_ADDRESSING; excp = PGM_ADDRESSING;
tec = 0; /* unused */
fail = 1; fail = 1;
} }
@ -178,6 +179,10 @@ bool s390_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
} }
if (excp) { if (excp) {
if (excp != PGM_ADDRESSING) {
stq_phys(env_cpu(env)->as,
env->psa + offsetof(LowCore, trans_exc_code), tec);
}
trigger_pgm_exception(env, excp, ILEN_AUTO); trigger_pgm_exception(env, excp, ILEN_AUTO);
} }
cpu_restore_state(cs, retaddr, true); cpu_restore_state(cs, retaddr, true);