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target/openrisc: Increase the TLB size 

The architecture supports 128 TLB entries.  There is no reason
not to provide all of them.  In the process we need to fix a
bug that failed to parameterize the configuration register that
tells the operating system the number of entries.

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>

---
v2:
  - Change VMState version.
This commit is contained in:
Richard Henderson 2018-05-22 22:04:46 -07:00 committed by Stafford Horne
parent 5ce5dad352
commit 1cc9e5d896
3 changed files with 7 additions and 6 deletions
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6
target/openrisc/cpu.c
View File

@ -57,8 +57,10 @@ static void openrisc_cpu_reset(CPUState *s)
cpu->env.upr = UPR_UP | UPR_DMP | UPR_IMP | UPR_PICP | UPR_TTP |
UPR_PMP;
cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2)) | (DMMUCFGR_NTS & (6 << 2));
cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2)) | (IMMUCFGR_NTS & (6 << 2));
cpu->env.dmmucfgr = (DMMUCFGR_NTW & (0 << 2))
| (DMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
cpu->env.immucfgr = (IMMUCFGR_NTW & (0 << 2))
| (IMMUCFGR_NTS & (ctz32(TLB_SIZE) << 2));
#ifndef CONFIG_USER_ONLY
cpu->env.picmr = 0x00000000;

2
target/openrisc/cpu.h
View File

@ -222,7 +222,7 @@ enum {
/* TLB size */
enum {
TLB_SIZE = 64,
TLB_SIZE = 128,
TLB_MASK = TLB_SIZE - 1,
};

5
target/openrisc/machine.c
View File

@ -38,9 +38,8 @@ static const VMStateDescription vmstate_tlb_entry = {
static const VMStateDescription vmstate_cpu_tlb = {
.name = "cpu_tlb",
.version_id = 1,
.minimum_version_id = 1,
.minimum_version_id_old = 1,
.version_id = 2,
.minimum_version_id = 2,
.fields = (VMStateField[]) {
VMSTATE_STRUCT_ARRAY(itlb, CPUOpenRISCTLBContext, TLB_SIZE, 0,
vmstate_tlb_entry, OpenRISCTLBEntry),