mirror of https://gitee.com/openkylin/qemu.git
target-lm32: fixes
-----BEGIN PGP SIGNATURE----- Version: GnuPG v1.4.12 (GNU/Linux) iEYEABECAAYFAlLxNdwACgkQEdFA3D+Yo3h0MQCgkqd4o4LdamOYxQqP0CgD+ET8 QFgAn19l7zj69bPiYEsl1kPxinIduZnd =ff/s -----END PGP SIGNATURE----- Merge remote-tracking branch 'remotes/mwalle/tags/lm32-fixes/20140204' into staging target-lm32: fixes # gpg: Signature made Tue 04 Feb 2014 18:47:56 GMT using DSA key ID 3F98A378 # gpg: Can't check signature: public key not found * remotes/mwalle/tags/lm32-fixes/20140204: hw/lm32: print error if cpu model is not found target-lm32: stop VM on illegal or unknown instruction lm32_sys: dump cpu state if test case fails lm32_sys: print test result on stderr target-lm32: add breakpoint/watchpoint support target-lm32: move model features to LM32CPU target-lm32: kill cpu_abort() calls milkymist-vgafb: swap pixel data in source buffer lm32_uart/lm32_juart: use qemu_chr_fe_write_all() milkymist-uart: use qemu_chr_fe_write_all() instead of qemu_chr_fe_write() tests: lm32: new rule for single test cases lm32_sys: increase test case name length limit Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Peter Maydell
commit
1f6b12f75f
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@ -75,7 +75,7 @@ void lm32_juart_set_jtx(DeviceState *d, uint32_t jtx)
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s->jtx = jtx;
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if (s->chr) {
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qemu_chr_fe_write(s->chr, &ch, 1);
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qemu_chr_fe_write_all(s->chr, &ch, 1);
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}
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}
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@ -177,7 +177,7 @@ static void uart_write(void *opaque, hwaddr addr,
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switch (addr) {
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case R_RXTX:
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if (s->chr) {
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qemu_chr_fe_write(s->chr, &ch, 1);
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qemu_chr_fe_write_all(s->chr, &ch, 1);
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}
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break;
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case R_IER:
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@ -124,7 +124,7 @@ static void uart_write(void *opaque, hwaddr addr, uint64_t value,
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switch (addr) {
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case R_RXTX:
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if (s->chr) {
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qemu_chr_fe_write(s->chr, &ch, 1);
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qemu_chr_fe_write_all(s->chr, &ch, 1);
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}
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s->regs[R_STAT] |= STAT_TX_EVT;
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break;
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@ -61,7 +61,7 @@ static void glue(draw_line_, BITS)(void *opaque, uint8_t *d, const uint8_t *s,
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uint8_t r, g, b;
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while (width--) {
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memcpy(&rgb565, s, sizeof(rgb565));
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rgb565 = lduw_be_p(s);
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r = ((rgb565 >> 11) & 0x1f) << 3;
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g = ((rgb565 >> 5) & 0x3f) << 2;
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b = ((rgb565 >> 0) & 0x1f) << 3;
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@ -101,6 +101,11 @@ static void lm32_evr_init(QEMUMachineInitArgs *args)
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cpu_model = "lm32-full";
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}
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cpu = cpu_lm32_init(cpu_model);
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if (cpu == NULL) {
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fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
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exit(1);
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}
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env = &cpu->env;
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reset_info->cpu = cpu;
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@ -198,6 +203,11 @@ static void lm32_uclinux_init(QEMUMachineInitArgs *args)
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cpu_model = "lm32-full";
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}
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cpu = cpu_lm32_init(cpu_model);
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if (cpu == NULL) {
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fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
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exit(1);
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}
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env = &cpu->env;
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reset_info->cpu = cpu;
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@ -108,6 +108,11 @@ milkymist_init(QEMUMachineInitArgs *args)
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cpu_model = "lm32-full";
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}
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cpu = cpu_lm32_init(cpu_model);
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if (cpu == NULL) {
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fprintf(stderr, "qemu: unable to find CPU '%s'\n", cpu_model);
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exit(1);
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}
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env = &cpu->env;
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reset_info->cpu = cpu;
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@ -42,7 +42,7 @@ enum {
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R_MAX
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};
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#define MAX_TESTNAME_LEN 16
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#define MAX_TESTNAME_LEN 32
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#define TYPE_LM32_SYS "lm32-sys"
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#define LM32_SYS(obj) OBJECT_CHECK(LM32SysState, (obj), TYPE_LM32_SYS)
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@ -80,7 +80,11 @@ static void sys_write(void *opaque, hwaddr addr,
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case R_PASSFAIL:
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s->regs[addr] = value;
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testname = (char *)s->testname;
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qemu_log("TC %-16s %s\n", testname, (value) ? "FAILED" : "OK");
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fprintf(stderr, "TC %-*s %s\n", MAX_TESTNAME_LEN,
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testname, (value) ? "FAILED" : "OK");
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if (value) {
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cpu_dump_state(qemu_get_cpu(0), stderr, fprintf, 0);
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}
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break;
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case R_TESTNAME:
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s->regs[addr] = value;
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@ -1,3 +1 @@
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* disassembler (lm32-dis.c)
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* linux-user emulation
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* native bp/wp emulation (?)
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@ -60,6 +60,12 @@ typedef struct LM32CPU {
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/*< public >*/
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CPULM32State env;
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uint32_t revision;
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uint8_t num_interrupts;
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uint8_t num_breakpoints;
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uint8_t num_watchpoints;
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uint32_t features;
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} LM32CPU;
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static inline LM32CPU *lm32_env_get_cpu(CPULM32State *env)
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@ -29,6 +29,87 @@ static void lm32_cpu_set_pc(CPUState *cs, vaddr value)
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cpu->env.pc = value;
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}
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/* Sort alphabetically by type name. */
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static gint lm32_cpu_list_compare(gconstpointer a, gconstpointer b)
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{
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ObjectClass *class_a = (ObjectClass *)a;
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ObjectClass *class_b = (ObjectClass *)b;
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const char *name_a, *name_b;
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name_a = object_class_get_name(class_a);
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name_b = object_class_get_name(class_b);
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return strcmp(name_a, name_b);
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}
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static void lm32_cpu_list_entry(gpointer data, gpointer user_data)
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{
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ObjectClass *oc = data;
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CPUListState *s = user_data;
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const char *typename = object_class_get_name(oc);
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char *name;
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name = g_strndup(typename, strlen(typename) - strlen("-" TYPE_LM32_CPU));
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(*s->cpu_fprintf)(s->file, " %s\n", name);
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g_free(name);
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}
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void lm32_cpu_list(FILE *f, fprintf_function cpu_fprintf)
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{
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CPUListState s = {
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.file = f,
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.cpu_fprintf = cpu_fprintf,
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};
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GSList *list;
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list = object_class_get_list(TYPE_LM32_CPU, false);
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list = g_slist_sort(list, lm32_cpu_list_compare);
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(*cpu_fprintf)(f, "Available CPUs:\n");
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g_slist_foreach(list, lm32_cpu_list_entry, &s);
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g_slist_free(list);
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}
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static void lm32_cpu_init_cfg_reg(LM32CPU *cpu)
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{
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CPULM32State *env = &cpu->env;
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uint32_t cfg = 0;
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if (cpu->features & LM32_FEATURE_MULTIPLY) {
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cfg |= CFG_M;
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}
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if (cpu->features & LM32_FEATURE_DIVIDE) {
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cfg |= CFG_D;
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}
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if (cpu->features & LM32_FEATURE_SHIFT) {
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cfg |= CFG_S;
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}
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if (cpu->features & LM32_FEATURE_SIGN_EXTEND) {
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cfg |= CFG_X;
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}
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if (cpu->features & LM32_FEATURE_I_CACHE) {
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cfg |= CFG_IC;
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}
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if (cpu->features & LM32_FEATURE_D_CACHE) {
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cfg |= CFG_DC;
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}
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if (cpu->features & LM32_FEATURE_CYCLE_COUNT) {
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cfg |= CFG_CC;
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}
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cfg |= (cpu->num_interrupts << CFG_INT_SHIFT);
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cfg |= (cpu->num_breakpoints << CFG_BP_SHIFT);
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cfg |= (cpu->num_watchpoints << CFG_WP_SHIFT);
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cfg |= (cpu->revision << CFG_REV_SHIFT);
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env->cfg = cfg;
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}
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/* CPUClass::reset() */
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static void lm32_cpu_reset(CPUState *s)
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{
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@ -41,6 +122,7 @@ static void lm32_cpu_reset(CPUState *s)
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/* reset cpu state */
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memset(env, 0, offsetof(CPULM32State, breakpoints));
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lm32_cpu_init_cfg_reg(cpu);
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tlb_flush(env, 1);
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}
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@ -71,9 +153,95 @@ static void lm32_cpu_initfn(Object *obj)
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if (tcg_enabled() && !tcg_initialized) {
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tcg_initialized = true;
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lm32_translate_init();
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cpu_set_debug_excp_handler(lm32_debug_excp_handler);
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}
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}
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static void lm32_basic_cpu_initfn(Object *obj)
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{
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LM32CPU *cpu = LM32_CPU(obj);
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cpu->revision = 3;
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cpu->num_interrupts = 32;
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cpu->num_breakpoints = 4;
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cpu->num_watchpoints = 4;
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cpu->features = LM32_FEATURE_SHIFT
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| LM32_FEATURE_SIGN_EXTEND
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| LM32_FEATURE_CYCLE_COUNT;
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}
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static void lm32_standard_cpu_initfn(Object *obj)
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{
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LM32CPU *cpu = LM32_CPU(obj);
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cpu->revision = 3;
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cpu->num_interrupts = 32;
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cpu->num_breakpoints = 4;
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cpu->num_watchpoints = 4;
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cpu->features = LM32_FEATURE_MULTIPLY
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| LM32_FEATURE_DIVIDE
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| LM32_FEATURE_SHIFT
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| LM32_FEATURE_SIGN_EXTEND
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| LM32_FEATURE_I_CACHE
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| LM32_FEATURE_CYCLE_COUNT;
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}
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static void lm32_full_cpu_initfn(Object *obj)
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{
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LM32CPU *cpu = LM32_CPU(obj);
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cpu->revision = 3;
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cpu->num_interrupts = 32;
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cpu->num_breakpoints = 4;
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cpu->num_watchpoints = 4;
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cpu->features = LM32_FEATURE_MULTIPLY
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| LM32_FEATURE_DIVIDE
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| LM32_FEATURE_SHIFT
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| LM32_FEATURE_SIGN_EXTEND
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| LM32_FEATURE_I_CACHE
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| LM32_FEATURE_D_CACHE
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| LM32_FEATURE_CYCLE_COUNT;
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}
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typedef struct LM32CPUInfo {
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const char *name;
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void (*initfn)(Object *obj);
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} LM32CPUInfo;
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static const LM32CPUInfo lm32_cpus[] = {
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{
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.name = "lm32-basic",
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.initfn = lm32_basic_cpu_initfn,
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},
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{
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.name = "lm32-standard",
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.initfn = lm32_standard_cpu_initfn,
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},
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{
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.name = "lm32-full",
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.initfn = lm32_full_cpu_initfn,
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},
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};
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static ObjectClass *lm32_cpu_class_by_name(const char *cpu_model)
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{
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ObjectClass *oc;
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char *typename;
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if (cpu_model == NULL) {
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return NULL;
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}
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typename = g_strdup_printf("%s-" TYPE_LM32_CPU, cpu_model);
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oc = object_class_by_name(typename);
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g_free(typename);
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if (oc != NULL && (!object_class_dynamic_cast(oc, TYPE_LM32_CPU) ||
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object_class_is_abstract(oc))) {
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oc = NULL;
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}
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return oc;
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}
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static void lm32_cpu_class_init(ObjectClass *oc, void *data)
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{
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LM32CPUClass *lcc = LM32_CPU_CLASS(oc);
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@ -86,6 +254,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
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lcc->parent_reset = cc->reset;
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cc->reset = lm32_cpu_reset;
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cc->class_by_name = lm32_cpu_class_by_name;
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cc->do_interrupt = lm32_cpu_do_interrupt;
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cc->dump_state = lm32_cpu_dump_state;
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cc->set_pc = lm32_cpu_set_pc;
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@ -98,19 +267,36 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data)
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cc->gdb_num_core_regs = 32 + 7;
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}
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static void lm32_register_cpu_type(const LM32CPUInfo *info)
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{
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TypeInfo type_info = {
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.parent = TYPE_LM32_CPU,
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.instance_init = info->initfn,
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};
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type_info.name = g_strdup_printf("%s-" TYPE_LM32_CPU, info->name);
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type_register(&type_info);
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g_free((void *)type_info.name);
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}
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static const TypeInfo lm32_cpu_type_info = {
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.name = TYPE_LM32_CPU,
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.parent = TYPE_CPU,
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.instance_size = sizeof(LM32CPU),
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.instance_init = lm32_cpu_initfn,
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.abstract = false,
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.abstract = true,
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.class_size = sizeof(LM32CPUClass),
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.class_init = lm32_cpu_class_init,
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};
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static void lm32_cpu_register_types(void)
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{
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int i;
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type_register_static(&lm32_cpu_type_info);
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for (i = 0; i < ARRAY_SIZE(lm32_cpus); i++) {
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lm32_register_cpu_type(&lm32_cpus[i]);
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}
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}
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type_init(lm32_cpu_register_types)
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@ -163,8 +163,11 @@ struct CPULM32State {
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/* debug registers */
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uint32_t dc; /* debug control */
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uint32_t bp[4]; /* breakpoint addresses */
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uint32_t wp[4]; /* watchpoint addresses */
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uint32_t bp[4]; /* breakpoints */
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uint32_t wp[4]; /* watchpoints */
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CPUBreakpoint * cpu_breakpoint[4];
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CPUWatchpoint * cpu_watchpoint[4];
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CPU_COMMON
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@ -177,25 +180,42 @@ struct CPULM32State {
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DeviceState *juart_state;
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/* processor core features */
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uint32_t features;
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uint32_t flags;
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uint8_t num_bps;
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uint8_t num_wps;
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};
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typedef enum {
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LM32_WP_DISABLED = 0,
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LM32_WP_READ,
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LM32_WP_WRITE,
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LM32_WP_READ_WRITE,
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} lm32_wp_t;
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static inline lm32_wp_t lm32_wp_type(uint32_t dc, int idx)
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{
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assert(idx < 4);
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return (dc >> (idx+1)*2) & 0x3;
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}
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#include "cpu-qom.h"
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LM32CPU *cpu_lm32_init(const char *cpu_model);
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void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf);
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int cpu_lm32_exec(CPULM32State *s);
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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signal handlers to inform the virtual CPU of exceptions. non zero
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is returned if the signal was handled by the virtual CPU. */
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int cpu_lm32_signal_handler(int host_signum, void *pinfo,
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void *puc);
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void lm32_cpu_list(FILE *f, fprintf_function cpu_fprintf);
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void lm32_translate_init(void);
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void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value);
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void QEMU_NORETURN raise_exception(CPULM32State *env, int index);
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void lm32_debug_excp_handler(CPULM32State *env);
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void lm32_breakpoint_insert(CPULM32State *env, int index, target_ulong address);
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void lm32_breakpoint_remove(CPULM32State *env, int index);
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void lm32_watchpoint_insert(CPULM32State *env, int index, target_ulong address,
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lm32_wp_t wp_type);
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void lm32_watchpoint_remove(CPULM32State *env, int index);
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static inline CPULM32State *cpu_init(const char *cpu_model)
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{
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@ -206,7 +226,7 @@ static inline CPULM32State *cpu_init(const char *cpu_model)
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return &cpu->env;
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}
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#define cpu_list cpu_lm32_list
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#define cpu_list lm32_cpu_list
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#define cpu_exec cpu_lm32_exec
|
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#define cpu_gen_code cpu_lm32_gen_code
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#define cpu_signal_handler cpu_lm32_signal_handler
|
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|
|
@ -49,6 +49,96 @@ hwaddr lm32_cpu_get_phys_page_debug(CPUState *cs, vaddr addr)
|
|||
}
|
||||
}
|
||||
|
||||
void lm32_breakpoint_insert(CPULM32State *env, int idx, target_ulong address)
|
||||
{
|
||||
cpu_breakpoint_insert(env, address, BP_CPU, &env->cpu_breakpoint[idx]);
|
||||
}
|
||||
|
||||
void lm32_breakpoint_remove(CPULM32State *env, int idx)
|
||||
{
|
||||
if (!env->cpu_breakpoint[idx]) {
|
||||
return;
|
||||
}
|
||||
|
||||
cpu_breakpoint_remove_by_ref(env, env->cpu_breakpoint[idx]);
|
||||
env->cpu_breakpoint[idx] = NULL;
|
||||
}
|
||||
|
||||
void lm32_watchpoint_insert(CPULM32State *env, int idx, target_ulong address,
|
||||
lm32_wp_t wp_type)
|
||||
{
|
||||
int flags = 0;
|
||||
|
||||
switch (wp_type) {
|
||||
case LM32_WP_DISABLED:
|
||||
/* nothing to to */
|
||||
break;
|
||||
case LM32_WP_READ:
|
||||
flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_READ;
|
||||
break;
|
||||
case LM32_WP_WRITE:
|
||||
flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_WRITE;
|
||||
break;
|
||||
case LM32_WP_READ_WRITE:
|
||||
flags = BP_CPU | BP_STOP_BEFORE_ACCESS | BP_MEM_ACCESS;
|
||||
break;
|
||||
}
|
||||
|
||||
if (flags != 0) {
|
||||
cpu_watchpoint_insert(env, address, 1, flags,
|
||||
&env->cpu_watchpoint[idx]);
|
||||
}
|
||||
}
|
||||
|
||||
void lm32_watchpoint_remove(CPULM32State *env, int idx)
|
||||
{
|
||||
if (!env->cpu_watchpoint[idx]) {
|
||||
return;
|
||||
}
|
||||
|
||||
cpu_watchpoint_remove_by_ref(env, env->cpu_watchpoint[idx]);
|
||||
env->cpu_watchpoint[idx] = NULL;
|
||||
}
|
||||
|
||||
static bool check_watchpoints(CPULM32State *env)
|
||||
{
|
||||
LM32CPU *cpu = lm32_env_get_cpu(env);
|
||||
int i;
|
||||
|
||||
for (i = 0; i < cpu->num_watchpoints; i++) {
|
||||
if (env->cpu_watchpoint[i] &&
|
||||
env->cpu_watchpoint[i]->flags & BP_WATCHPOINT_HIT) {
|
||||
return true;
|
||||
}
|
||||
}
|
||||
return false;
|
||||
}
|
||||
|
||||
void lm32_debug_excp_handler(CPULM32State *env)
|
||||
{
|
||||
CPUBreakpoint *bp;
|
||||
|
||||
if (env->watchpoint_hit) {
|
||||
if (env->watchpoint_hit->flags & BP_CPU) {
|
||||
env->watchpoint_hit = NULL;
|
||||
if (check_watchpoints(env)) {
|
||||
raise_exception(env, EXCP_WATCHPOINT);
|
||||
} else {
|
||||
cpu_resume_from_signal(env, NULL);
|
||||
}
|
||||
}
|
||||
} else {
|
||||
QTAILQ_FOREACH(bp, &env->breakpoints, entry) {
|
||||
if (bp->pc == env->pc) {
|
||||
if (bp->flags & BP_CPU) {
|
||||
raise_exception(env, EXCP_BREAKPOINT);
|
||||
}
|
||||
break;
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void lm32_cpu_do_interrupt(CPUState *cs)
|
||||
{
|
||||
LM32CPU *cpu = LM32_CPU(cs);
|
||||
|
|
@ -90,136 +180,16 @@ void lm32_cpu_do_interrupt(CPUState *cs)
|
|||
}
|
||||
}
|
||||
|
||||
typedef struct {
|
||||
const char *name;
|
||||
uint32_t revision;
|
||||
uint8_t num_interrupts;
|
||||
uint8_t num_breakpoints;
|
||||
uint8_t num_watchpoints;
|
||||
uint32_t features;
|
||||
} LM32Def;
|
||||
|
||||
static const LM32Def lm32_defs[] = {
|
||||
{
|
||||
.name = "lm32-basic",
|
||||
.revision = 3,
|
||||
.num_interrupts = 32,
|
||||
.num_breakpoints = 4,
|
||||
.num_watchpoints = 4,
|
||||
.features = (LM32_FEATURE_SHIFT
|
||||
| LM32_FEATURE_SIGN_EXTEND
|
||||
| LM32_FEATURE_CYCLE_COUNT),
|
||||
},
|
||||
{
|
||||
.name = "lm32-standard",
|
||||
.revision = 3,
|
||||
.num_interrupts = 32,
|
||||
.num_breakpoints = 4,
|
||||
.num_watchpoints = 4,
|
||||
.features = (LM32_FEATURE_MULTIPLY
|
||||
| LM32_FEATURE_DIVIDE
|
||||
| LM32_FEATURE_SHIFT
|
||||
| LM32_FEATURE_SIGN_EXTEND
|
||||
| LM32_FEATURE_I_CACHE
|
||||
| LM32_FEATURE_CYCLE_COUNT),
|
||||
},
|
||||
{
|
||||
.name = "lm32-full",
|
||||
.revision = 3,
|
||||
.num_interrupts = 32,
|
||||
.num_breakpoints = 4,
|
||||
.num_watchpoints = 4,
|
||||
.features = (LM32_FEATURE_MULTIPLY
|
||||
| LM32_FEATURE_DIVIDE
|
||||
| LM32_FEATURE_SHIFT
|
||||
| LM32_FEATURE_SIGN_EXTEND
|
||||
| LM32_FEATURE_I_CACHE
|
||||
| LM32_FEATURE_D_CACHE
|
||||
| LM32_FEATURE_CYCLE_COUNT),
|
||||
}
|
||||
};
|
||||
|
||||
void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf)
|
||||
{
|
||||
int i;
|
||||
|
||||
cpu_fprintf(f, "Available CPUs:\n");
|
||||
for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) {
|
||||
cpu_fprintf(f, " %s\n", lm32_defs[i].name);
|
||||
}
|
||||
}
|
||||
|
||||
static const LM32Def *cpu_lm32_find_by_name(const char *name)
|
||||
{
|
||||
int i;
|
||||
|
||||
for (i = 0; i < ARRAY_SIZE(lm32_defs); i++) {
|
||||
if (strcasecmp(name, lm32_defs[i].name) == 0) {
|
||||
return &lm32_defs[i];
|
||||
}
|
||||
}
|
||||
|
||||
return NULL;
|
||||
}
|
||||
|
||||
static uint32_t cfg_by_def(const LM32Def *def)
|
||||
{
|
||||
uint32_t cfg = 0;
|
||||
|
||||
if (def->features & LM32_FEATURE_MULTIPLY) {
|
||||
cfg |= CFG_M;
|
||||
}
|
||||
|
||||
if (def->features & LM32_FEATURE_DIVIDE) {
|
||||
cfg |= CFG_D;
|
||||
}
|
||||
|
||||
if (def->features & LM32_FEATURE_SHIFT) {
|
||||
cfg |= CFG_S;
|
||||
}
|
||||
|
||||
if (def->features & LM32_FEATURE_SIGN_EXTEND) {
|
||||
cfg |= CFG_X;
|
||||
}
|
||||
|
||||
if (def->features & LM32_FEATURE_I_CACHE) {
|
||||
cfg |= CFG_IC;
|
||||
}
|
||||
|
||||
if (def->features & LM32_FEATURE_D_CACHE) {
|
||||
cfg |= CFG_DC;
|
||||
}
|
||||
|
||||
if (def->features & LM32_FEATURE_CYCLE_COUNT) {
|
||||
cfg |= CFG_CC;
|
||||
}
|
||||
|
||||
cfg |= (def->num_interrupts << CFG_INT_SHIFT);
|
||||
cfg |= (def->num_breakpoints << CFG_BP_SHIFT);
|
||||
cfg |= (def->num_watchpoints << CFG_WP_SHIFT);
|
||||
cfg |= (def->revision << CFG_REV_SHIFT);
|
||||
|
||||
return cfg;
|
||||
}
|
||||
|
||||
LM32CPU *cpu_lm32_init(const char *cpu_model)
|
||||
{
|
||||
LM32CPU *cpu;
|
||||
CPULM32State *env;
|
||||
const LM32Def *def;
|
||||
ObjectClass *oc;
|
||||
|
||||
def = cpu_lm32_find_by_name(cpu_model);
|
||||
if (!def) {
|
||||
oc = cpu_class_by_name(TYPE_LM32_CPU, cpu_model);
|
||||
if (oc == NULL) {
|
||||
return NULL;
|
||||
}
|
||||
|
||||
cpu = LM32_CPU(object_new(TYPE_LM32_CPU));
|
||||
env = &cpu->env;
|
||||
|
||||
env->features = def->features;
|
||||
env->num_bps = def->num_breakpoints;
|
||||
env->num_wps = def->num_watchpoints;
|
||||
env->cfg = cfg_by_def(def);
|
||||
cpu = LM32_CPU(object_new(object_class_get_name(oc)));
|
||||
|
||||
object_property_set_bool(OBJECT(cpu), true, "realized", NULL);
|
||||
|
||||
|
|
|
|||
|
|
@ -2,6 +2,9 @@
|
|||
|
||||
DEF_HELPER_2(raise_exception, void, env, i32)
|
||||
DEF_HELPER_1(hlt, void, env)
|
||||
DEF_HELPER_3(wcsr_bp, void, env, i32, i32)
|
||||
DEF_HELPER_3(wcsr_wp, void, env, i32, i32)
|
||||
DEF_HELPER_2(wcsr_dc, void, env, i32)
|
||||
DEF_HELPER_2(wcsr_im, void, env, i32)
|
||||
DEF_HELPER_2(wcsr_ip, void, env, i32)
|
||||
DEF_HELPER_2(wcsr_jtx, void, env, i32)
|
||||
|
|
@ -10,5 +13,6 @@ DEF_HELPER_1(rcsr_im, i32, env)
|
|||
DEF_HELPER_1(rcsr_ip, i32, env)
|
||||
DEF_HELPER_1(rcsr_jtx, i32, env)
|
||||
DEF_HELPER_1(rcsr_jrx, i32, env)
|
||||
DEF_HELPER_1(ill, void, env)
|
||||
|
||||
#include "exec/def-helper.h"
|
||||
|
|
|
|||
|
|
@ -8,6 +8,10 @@
|
|||
|
||||
#include "exec/softmmu_exec.h"
|
||||
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
#include "sysemu/sysemu.h"
|
||||
#endif
|
||||
|
||||
#if !defined(CONFIG_USER_ONLY)
|
||||
#define MMUSUFFIX _mmu
|
||||
#define SHIFT 0
|
||||
|
|
@ -19,12 +23,17 @@
|
|||
#define SHIFT 3
|
||||
#include "exec/softmmu_template.h"
|
||||
|
||||
void HELPER(raise_exception)(CPULM32State *env, uint32_t index)
|
||||
void raise_exception(CPULM32State *env, int index)
|
||||
{
|
||||
env->exception_index = index;
|
||||
cpu_loop_exit(env);
|
||||
}
|
||||
|
||||
void HELPER(raise_exception)(CPULM32State *env, uint32_t index)
|
||||
{
|
||||
raise_exception(env, index);
|
||||
}
|
||||
|
||||
void HELPER(hlt)(CPULM32State *env)
|
||||
{
|
||||
CPUState *cs = CPU(lm32_env_get_cpu(env));
|
||||
|
|
@ -34,6 +43,70 @@ void HELPER(hlt)(CPULM32State *env)
|
|||
cpu_loop_exit(env);
|
||||
}
|
||||
|
||||
void HELPER(ill)(CPULM32State *env)
|
||||
{
|
||||
#ifndef CONFIG_USER_ONLY
|
||||
CPUState *cs = CPU(lm32_env_get_cpu(env));
|
||||
fprintf(stderr, "VM paused due to illegal instruction. "
|
||||
"Connect a debugger or switch to the monitor console "
|
||||
"to find out more.\n");
|
||||
qemu_system_vmstop_request(RUN_STATE_PAUSED);
|
||||
cs->halted = 1;
|
||||
raise_exception(env, EXCP_HALTED);
|
||||
#endif
|
||||
}
|
||||
|
||||
void HELPER(wcsr_bp)(CPULM32State *env, uint32_t bp, uint32_t idx)
|
||||
{
|
||||
uint32_t addr = bp & ~1;
|
||||
|
||||
assert(idx < 4);
|
||||
|
||||
env->bp[idx] = bp;
|
||||
lm32_breakpoint_remove(env, idx);
|
||||
if (bp & 1) {
|
||||
lm32_breakpoint_insert(env, idx, addr);
|
||||
}
|
||||
}
|
||||
|
||||
void HELPER(wcsr_wp)(CPULM32State *env, uint32_t wp, uint32_t idx)
|
||||
{
|
||||
lm32_wp_t wp_type;
|
||||
|
||||
assert(idx < 4);
|
||||
|
||||
env->wp[idx] = wp;
|
||||
|
||||
wp_type = lm32_wp_type(env->dc, idx);
|
||||
lm32_watchpoint_remove(env, idx);
|
||||
if (wp_type != LM32_WP_DISABLED) {
|
||||
lm32_watchpoint_insert(env, idx, wp, wp_type);
|
||||
}
|
||||
}
|
||||
|
||||
void HELPER(wcsr_dc)(CPULM32State *env, uint32_t dc)
|
||||
{
|
||||
uint32_t old_dc;
|
||||
int i;
|
||||
lm32_wp_t old_type;
|
||||
lm32_wp_t new_type;
|
||||
|
||||
old_dc = env->dc;
|
||||
env->dc = dc;
|
||||
|
||||
for (i = 0; i < 4; i++) {
|
||||
old_type = lm32_wp_type(old_dc, i);
|
||||
new_type = lm32_wp_type(dc, i);
|
||||
|
||||
if (old_type != new_type) {
|
||||
lm32_watchpoint_remove(env, i);
|
||||
if (new_type != LM32_WP_DISABLED) {
|
||||
lm32_watchpoint_insert(env, i, env->wp[i], new_type);
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
void HELPER(wcsr_im)(CPULM32State *env, uint32_t im)
|
||||
{
|
||||
lm32_pic_set_im(env->pic_state, im);
|
||||
|
|
|
|||
|
|
@ -64,7 +64,6 @@ enum {
|
|||
|
||||
/* This is the state at translation time. */
|
||||
typedef struct DisasContext {
|
||||
CPULM32State *env;
|
||||
target_ulong pc;
|
||||
|
||||
/* Decoder. */
|
||||
|
|
@ -80,9 +79,12 @@ typedef struct DisasContext {
|
|||
unsigned int tb_flags, synced_flags; /* tb dependent flags. */
|
||||
int is_jmp;
|
||||
|
||||
int nr_nops;
|
||||
struct TranslationBlock *tb;
|
||||
int singlestep_enabled;
|
||||
|
||||
uint32_t features;
|
||||
uint8_t num_breakpoints;
|
||||
uint8_t num_watchpoints;
|
||||
} DisasContext;
|
||||
|
||||
static const char *regnames[] = {
|
||||
|
|
@ -120,6 +122,12 @@ static inline void t_gen_raise_exception(DisasContext *dc, uint32_t index)
|
|||
tcg_temp_free_i32(tmp);
|
||||
}
|
||||
|
||||
static inline void t_gen_illegal_insn(DisasContext *dc)
|
||||
{
|
||||
tcg_gen_movi_tl(cpu_pc, dc->pc);
|
||||
gen_helper_ill(cpu_env);
|
||||
}
|
||||
|
||||
static void gen_goto_tb(DisasContext *dc, int n, target_ulong dest)
|
||||
{
|
||||
TranslationBlock *tb;
|
||||
|
|
@ -421,8 +429,10 @@ static void dec_divu(DisasContext *dc)
|
|||
|
||||
LOG_DIS("divu r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
||||
|
||||
if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
|
||||
cpu_abort(dc->env, "hardware divider is not available\n");
|
||||
if (!(dc->features & LM32_FEATURE_DIVIDE)) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "hardware divider is not available\n");
|
||||
t_gen_illegal_insn(dc);
|
||||
return;
|
||||
}
|
||||
|
||||
l1 = gen_new_label();
|
||||
|
|
@ -499,8 +509,10 @@ static void dec_modu(DisasContext *dc)
|
|||
|
||||
LOG_DIS("modu r%d, r%d, %d\n", dc->r2, dc->r0, dc->r1);
|
||||
|
||||
if (!(dc->env->features & LM32_FEATURE_DIVIDE)) {
|
||||
cpu_abort(dc->env, "hardware divider is not available\n");
|
||||
if (!(dc->features & LM32_FEATURE_DIVIDE)) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "hardware divider is not available\n");
|
||||
t_gen_illegal_insn(dc);
|
||||
return;
|
||||
}
|
||||
|
||||
l1 = gen_new_label();
|
||||
|
|
@ -520,8 +532,11 @@ static void dec_mul(DisasContext *dc)
|
|||
LOG_DIS("mul r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
||||
}
|
||||
|
||||
if (!(dc->env->features & LM32_FEATURE_MULTIPLY)) {
|
||||
cpu_abort(dc->env, "hardware multiplier is not available\n");
|
||||
if (!(dc->features & LM32_FEATURE_MULTIPLY)) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"hardware multiplier is not available\n");
|
||||
t_gen_illegal_insn(dc);
|
||||
return;
|
||||
}
|
||||
|
||||
if (dc->format == OP_FMT_RI) {
|
||||
|
|
@ -585,20 +600,21 @@ static void dec_orhi(DisasContext *dc)
|
|||
|
||||
static void dec_scall(DisasContext *dc)
|
||||
{
|
||||
if (dc->imm5 == 7) {
|
||||
LOG_DIS("scall\n");
|
||||
} else if (dc->imm5 == 2) {
|
||||
switch (dc->imm5) {
|
||||
case 2:
|
||||
LOG_DIS("break\n");
|
||||
} else {
|
||||
cpu_abort(dc->env, "invalid opcode\n");
|
||||
}
|
||||
|
||||
if (dc->imm5 == 7) {
|
||||
tcg_gen_movi_tl(cpu_pc, dc->pc);
|
||||
t_gen_raise_exception(dc, EXCP_SYSTEMCALL);
|
||||
} else {
|
||||
tcg_gen_movi_tl(cpu_pc, dc->pc);
|
||||
t_gen_raise_exception(dc, EXCP_BREAKPOINT);
|
||||
break;
|
||||
case 7:
|
||||
LOG_DIS("scall\n");
|
||||
tcg_gen_movi_tl(cpu_pc, dc->pc);
|
||||
t_gen_raise_exception(dc, EXCP_SYSTEMCALL);
|
||||
break;
|
||||
default:
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "invalid opcode @0x%x", dc->pc);
|
||||
t_gen_illegal_insn(dc);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
||||
|
|
@ -647,10 +663,10 @@ static void dec_rcsr(DisasContext *dc)
|
|||
case CSR_WP1:
|
||||
case CSR_WP2:
|
||||
case CSR_WP3:
|
||||
cpu_abort(dc->env, "invalid read access csr=%x\n", dc->csr);
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "invalid read access csr=%x\n", dc->csr);
|
||||
break;
|
||||
default:
|
||||
cpu_abort(dc->env, "read_csr: unknown csr=%x\n", dc->csr);
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "read_csr: unknown csr=%x\n", dc->csr);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -671,8 +687,11 @@ static void dec_sextb(DisasContext *dc)
|
|||
{
|
||||
LOG_DIS("sextb r%d, r%d\n", dc->r2, dc->r0);
|
||||
|
||||
if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
|
||||
cpu_abort(dc->env, "hardware sign extender is not available\n");
|
||||
if (!(dc->features & LM32_FEATURE_SIGN_EXTEND)) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"hardware sign extender is not available\n");
|
||||
t_gen_illegal_insn(dc);
|
||||
return;
|
||||
}
|
||||
|
||||
tcg_gen_ext8s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
|
||||
|
|
@ -682,8 +701,11 @@ static void dec_sexth(DisasContext *dc)
|
|||
{
|
||||
LOG_DIS("sexth r%d, r%d\n", dc->r2, dc->r0);
|
||||
|
||||
if (!(dc->env->features & LM32_FEATURE_SIGN_EXTEND)) {
|
||||
cpu_abort(dc->env, "hardware sign extender is not available\n");
|
||||
if (!(dc->features & LM32_FEATURE_SIGN_EXTEND)) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"hardware sign extender is not available\n");
|
||||
t_gen_illegal_insn(dc);
|
||||
return;
|
||||
}
|
||||
|
||||
tcg_gen_ext16s_tl(cpu_R[dc->r2], cpu_R[dc->r0]);
|
||||
|
|
@ -709,8 +731,10 @@ static void dec_sl(DisasContext *dc)
|
|||
LOG_DIS("sl r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
||||
}
|
||||
|
||||
if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
|
||||
cpu_abort(dc->env, "hardware shifter is not available\n");
|
||||
if (!(dc->features & LM32_FEATURE_SHIFT)) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "hardware shifter is not available\n");
|
||||
t_gen_illegal_insn(dc);
|
||||
return;
|
||||
}
|
||||
|
||||
if (dc->format == OP_FMT_RI) {
|
||||
|
|
@ -731,22 +755,32 @@ static void dec_sr(DisasContext *dc)
|
|||
LOG_DIS("sr r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
||||
}
|
||||
|
||||
if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
|
||||
/* The real CPU (w/o hardware shifter) only supports right shift by exactly
|
||||
* one bit */
|
||||
if (dc->format == OP_FMT_RI) {
|
||||
/* TODO: check r1 == 1 during runtime */
|
||||
} else {
|
||||
if (dc->imm5 != 1) {
|
||||
cpu_abort(dc->env, "hardware shifter is not available\n");
|
||||
if (!(dc->features & LM32_FEATURE_SHIFT) && (dc->imm5 != 1)) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"hardware shifter is not available\n");
|
||||
t_gen_illegal_insn(dc);
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (dc->format == OP_FMT_RI) {
|
||||
tcg_gen_sari_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
|
||||
} else {
|
||||
TCGv t0 = tcg_temp_new();
|
||||
int l1 = gen_new_label();
|
||||
int l2 = gen_new_label();
|
||||
TCGv t0 = tcg_temp_local_new();
|
||||
tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
|
||||
|
||||
if (!(dc->features & LM32_FEATURE_SHIFT)) {
|
||||
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 1, l1);
|
||||
t_gen_illegal_insn(dc);
|
||||
tcg_gen_br(l2);
|
||||
}
|
||||
|
||||
gen_set_label(l1);
|
||||
tcg_gen_sar_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
|
||||
gen_set_label(l2);
|
||||
|
||||
tcg_temp_free(t0);
|
||||
}
|
||||
}
|
||||
|
|
@ -759,22 +793,30 @@ static void dec_sru(DisasContext *dc)
|
|||
LOG_DIS("sru r%d, r%d, r%d\n", dc->r2, dc->r0, dc->r1);
|
||||
}
|
||||
|
||||
if (!(dc->env->features & LM32_FEATURE_SHIFT)) {
|
||||
if (dc->format == OP_FMT_RI) {
|
||||
/* TODO: check r1 == 1 during runtime */
|
||||
} else {
|
||||
if (dc->imm5 != 1) {
|
||||
cpu_abort(dc->env, "hardware shifter is not available\n");
|
||||
if (!(dc->features & LM32_FEATURE_SHIFT) && (dc->imm5 != 1)) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"hardware shifter is not available\n");
|
||||
t_gen_illegal_insn(dc);
|
||||
return;
|
||||
}
|
||||
}
|
||||
}
|
||||
|
||||
if (dc->format == OP_FMT_RI) {
|
||||
tcg_gen_shri_tl(cpu_R[dc->r1], cpu_R[dc->r0], dc->imm5);
|
||||
} else {
|
||||
TCGv t0 = tcg_temp_new();
|
||||
int l1 = gen_new_label();
|
||||
int l2 = gen_new_label();
|
||||
TCGv t0 = tcg_temp_local_new();
|
||||
tcg_gen_andi_tl(t0, cpu_R[dc->r1], 0x1f);
|
||||
|
||||
if (!(dc->features & LM32_FEATURE_SHIFT)) {
|
||||
tcg_gen_brcondi_tl(TCG_COND_EQ, t0, 1, l1);
|
||||
t_gen_illegal_insn(dc);
|
||||
tcg_gen_br(l2);
|
||||
}
|
||||
|
||||
gen_set_label(l1);
|
||||
tcg_gen_shr_tl(cpu_R[dc->r2], cpu_R[dc->r0], t0);
|
||||
gen_set_label(l2);
|
||||
|
||||
tcg_temp_free(t0);
|
||||
}
|
||||
}
|
||||
|
|
@ -802,7 +844,8 @@ static void dec_user(DisasContext *dc)
|
|||
{
|
||||
LOG_DIS("user");
|
||||
|
||||
cpu_abort(dc->env, "user insn undefined\n");
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "user instruction undefined\n");
|
||||
t_gen_illegal_insn(dc);
|
||||
}
|
||||
|
||||
static void dec_wcsr(DisasContext *dc)
|
||||
|
|
@ -860,34 +903,42 @@ static void dec_wcsr(DisasContext *dc)
|
|||
gen_helper_wcsr_jrx(cpu_env, cpu_R[dc->r1]);
|
||||
break;
|
||||
case CSR_DC:
|
||||
tcg_gen_mov_tl(cpu_dc, cpu_R[dc->r1]);
|
||||
gen_helper_wcsr_dc(cpu_env, cpu_R[dc->r1]);
|
||||
break;
|
||||
case CSR_BP0:
|
||||
case CSR_BP1:
|
||||
case CSR_BP2:
|
||||
case CSR_BP3:
|
||||
no = dc->csr - CSR_BP0;
|
||||
if (dc->env->num_bps <= no) {
|
||||
cpu_abort(dc->env, "breakpoint #%i is not available\n", no);
|
||||
if (dc->num_breakpoints <= no) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"breakpoint #%i is not available\n", no);
|
||||
t_gen_illegal_insn(dc);
|
||||
break;
|
||||
}
|
||||
tcg_gen_mov_tl(cpu_bp[no], cpu_R[dc->r1]);
|
||||
gen_helper_wcsr_bp(cpu_env, cpu_R[dc->r1], tcg_const_i32(no));
|
||||
break;
|
||||
case CSR_WP0:
|
||||
case CSR_WP1:
|
||||
case CSR_WP2:
|
||||
case CSR_WP3:
|
||||
no = dc->csr - CSR_WP0;
|
||||
if (dc->env->num_wps <= no) {
|
||||
cpu_abort(dc->env, "watchpoint #%i is not available\n", no);
|
||||
if (dc->num_watchpoints <= no) {
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"watchpoint #%i is not available\n", no);
|
||||
t_gen_illegal_insn(dc);
|
||||
break;
|
||||
}
|
||||
tcg_gen_mov_tl(cpu_wp[no], cpu_R[dc->r1]);
|
||||
gen_helper_wcsr_wp(cpu_env, cpu_R[dc->r1], tcg_const_i32(no));
|
||||
break;
|
||||
case CSR_CC:
|
||||
case CSR_CFG:
|
||||
cpu_abort(dc->env, "invalid write access csr=%x\n", dc->csr);
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "invalid write access csr=%x\n",
|
||||
dc->csr);
|
||||
break;
|
||||
default:
|
||||
cpu_abort(dc->env, "write_csr unknown csr=%x\n", dc->csr);
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "write_csr: unknown csr=%x\n",
|
||||
dc->csr);
|
||||
break;
|
||||
}
|
||||
}
|
||||
|
|
@ -933,7 +984,8 @@ static void dec_xor(DisasContext *dc)
|
|||
|
||||
static void dec_ill(DisasContext *dc)
|
||||
{
|
||||
cpu_abort(dc->env, "unknown opcode 0x%02x\n", dc->opcode);
|
||||
qemu_log_mask(LOG_GUEST_ERROR, "invalid opcode 0x%02x\n", dc->opcode);
|
||||
t_gen_illegal_insn(dc);
|
||||
}
|
||||
|
||||
typedef void (*DecoderInfo)(DisasContext *dc);
|
||||
|
|
@ -959,18 +1011,6 @@ static inline void decode(DisasContext *dc, uint32_t ir)
|
|||
dc->ir = ir;
|
||||
LOG_DIS("%8.8x\t", dc->ir);
|
||||
|
||||
/* try guessing 'empty' instruction memory, although it may be a valid
|
||||
* instruction sequence (eg. srui r0, r0, 0) */
|
||||
if (dc->ir) {
|
||||
dc->nr_nops = 0;
|
||||
} else {
|
||||
LOG_DIS("nr_nops=%d\t", dc->nr_nops);
|
||||
dc->nr_nops++;
|
||||
if (dc->nr_nops > 4) {
|
||||
cpu_abort(dc->env, "fetching nop sequence\n");
|
||||
}
|
||||
}
|
||||
|
||||
dc->opcode = EXTRACT_FIELD(ir, 26, 31);
|
||||
|
||||
dc->imm5 = EXTRACT_FIELD(ir, 0, 4);
|
||||
|
|
@ -1026,7 +1066,9 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
|
|||
int max_insns;
|
||||
|
||||
pc_start = tb->pc;
|
||||
dc->env = env;
|
||||
dc->features = cpu->features;
|
||||
dc->num_breakpoints = cpu->num_breakpoints;
|
||||
dc->num_watchpoints = cpu->num_watchpoints;
|
||||
dc->tb = tb;
|
||||
|
||||
gen_opc_end = tcg_ctx.gen_opc_buf + OPC_MAX_SIZE;
|
||||
|
|
@ -1034,10 +1076,11 @@ void gen_intermediate_code_internal(LM32CPU *cpu,
|
|||
dc->is_jmp = DISAS_NEXT;
|
||||
dc->pc = pc_start;
|
||||
dc->singlestep_enabled = cs->singlestep_enabled;
|
||||
dc->nr_nops = 0;
|
||||
|
||||
if (pc_start & 3) {
|
||||
cpu_abort(env, "LM32: unaligned PC=%x\n", pc_start);
|
||||
qemu_log_mask(LOG_GUEST_ERROR,
|
||||
"unaligned PC=%x. Ignoring lowest bits.\n", pc_start);
|
||||
pc_start &= ~3;
|
||||
}
|
||||
|
||||
next_page_start = (pc_start & TARGET_PAGE_MASK) + TARGET_PAGE_SIZE;
|
||||
|
|
|
|||
|
|
@ -96,10 +96,10 @@ all: build
|
|||
|
||||
build: $(CRT) $(TESTCASES)
|
||||
|
||||
check: $(CRT) $(SYS) $(TESTCASES)
|
||||
@for case in $(TESTCASES); do \
|
||||
$(SIM) $(SIMFLAGS) ./$$case; \
|
||||
done
|
||||
check: $(TESTCASES:test_%.tst=check_%)
|
||||
|
||||
check_%: test_%.tst $(CRT) $(SYS)
|
||||
$(SIM) $(SIMFLAGS) $<
|
||||
|
||||
clean:
|
||||
$(RM) -fr $(TESTCASES) $(CRT)
|
||||
|
|
|
|||
Loading…
Reference in New Issue