mirror of https://gitee.com/openkylin/qemu.git
pxa2xx_dma: port to qdev/vmstate
Signed-off-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com> Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>
This commit is contained in:
parent
47188700a4
commit
2115c01924
16
hw/pxa.h
16
hw/pxa.h
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@ -71,12 +71,8 @@ DeviceState *pxa2xx_gpio_init(target_phys_addr_t base,
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void pxa2xx_gpio_read_notifier(DeviceState *dev, qemu_irq handler);
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/* pxa2xx_dma.c */
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typedef struct PXA2xxDMAState PXA2xxDMAState;
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PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base,
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qemu_irq irq);
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PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base,
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qemu_irq irq);
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void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on);
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DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq);
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DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq);
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/* pxa2xx_lcd.c */
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typedef struct PXA2xxLCDState PXA2xxLCDState;
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@ -88,7 +84,8 @@ void pxa2xx_lcdc_oritentation(void *opaque, int angle);
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/* pxa2xx_mmci.c */
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typedef struct PXA2xxMMCIState PXA2xxMMCIState;
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PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
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BlockDriverState *bd, qemu_irq irq, void *dma);
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BlockDriverState *bd, qemu_irq irq,
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qemu_irq rx_dma, qemu_irq tx_dma);
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void pxa2xx_mmci_handlers(PXA2xxMMCIState *s, qemu_irq readonly,
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qemu_irq coverswitch);
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@ -123,7 +120,7 @@ typedef struct {
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CPUState *env;
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DeviceState *pic;
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qemu_irq reset;
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PXA2xxDMAState *dma;
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DeviceState *dma;
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DeviceState *gpio;
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PXA2xxLCDState *lcd;
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SSIBus **ssp;
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@ -181,7 +178,8 @@ typedef struct {
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struct PXA2xxI2SState {
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qemu_irq irq;
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PXA2xxDMAState *dma;
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qemu_irq rx_dma;
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qemu_irq tx_dma;
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void (*data_req)(void *, int, int);
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uint32_t control[2];
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45
hw/pxa2xx.c
45
hw/pxa2xx.c
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@ -1585,8 +1585,8 @@ static inline void pxa2xx_i2s_update(PXA2xxI2SState *i2s)
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tfs = (i2s->tx_len || i2s->fifo_len < SACR_TFTH(i2s->control[0])) &&
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i2s->enable && !SACR_DPRL(i2s->control[1]);
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pxa2xx_dma_request(i2s->dma, PXA2XX_RX_RQ_I2S, rfs);
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pxa2xx_dma_request(i2s->dma, PXA2XX_TX_RQ_I2S, tfs);
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qemu_set_irq(i2s->rx_dma, rfs);
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qemu_set_irq(i2s->tx_dma, tfs);
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i2s->status &= 0xe0;
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if (i2s->fifo_len < 16 || !i2s->enable)
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@ -1769,14 +1769,15 @@ static void pxa2xx_i2s_data_req(void *opaque, int tx, int rx)
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}
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static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base,
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qemu_irq irq, PXA2xxDMAState *dma)
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qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma)
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{
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int iomemtype;
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PXA2xxI2SState *s = (PXA2xxI2SState *)
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qemu_mallocz(sizeof(PXA2xxI2SState));
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s->irq = irq;
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s->dma = dma;
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s->rx_dma = rx_dma;
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s->tx_dma = tx_dma;
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s->data_req = pxa2xx_i2s_data_req;
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pxa2xx_i2s_reset(s);
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@ -1794,7 +1795,8 @@ static PXA2xxI2SState *pxa2xx_i2s_init(target_phys_addr_t base,
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/* PXA Fast Infra-red Communications Port */
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struct PXA2xxFIrState {
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qemu_irq irq;
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PXA2xxDMAState *dma;
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qemu_irq rx_dma;
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qemu_irq tx_dma;
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int enable;
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CharDriverState *chr;
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@ -1848,8 +1850,8 @@ static inline void pxa2xx_fir_update(PXA2xxFIrState *s)
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(s->status[0] & (1 << 1)); /* TUR */
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intr |= s->status[0] & 0x25; /* FRE, RAB, EIF */
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pxa2xx_dma_request(s->dma, PXA2XX_RX_RQ_ICP, (s->status[0] >> 4) & 1);
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pxa2xx_dma_request(s->dma, PXA2XX_TX_RQ_ICP, (s->status[0] >> 3) & 1);
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qemu_set_irq(s->rx_dma, (s->status[0] >> 4) & 1);
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qemu_set_irq(s->tx_dma, (s->status[0] >> 3) & 1);
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qemu_set_irq(s->irq, intr && s->enable);
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}
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@ -2028,7 +2030,7 @@ static int pxa2xx_fir_load(QEMUFile *f, void *opaque, int version_id)
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}
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static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
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qemu_irq irq, PXA2xxDMAState *dma,
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qemu_irq irq, qemu_irq rx_dma, qemu_irq tx_dma,
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CharDriverState *chr)
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{
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int iomemtype;
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@ -2036,7 +2038,8 @@ static PXA2xxFIrState *pxa2xx_fir_init(target_phys_addr_t base,
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qemu_mallocz(sizeof(PXA2xxFIrState));
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s->irq = irq;
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s->dma = dma;
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s->rx_dma = rx_dma;
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s->tx_dma = tx_dma;
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s->chr = chr;
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pxa2xx_fir_reset(s);
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@ -2116,7 +2119,9 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
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exit(1);
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}
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s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), s->dma);
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
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qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
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qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
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for (i = 0; pxa270_serial[i].io_base; i ++)
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if (serial_hds[i])
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@ -2134,7 +2139,9 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
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if (serial_hds[i])
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s->fir = pxa2xx_fir_init(0x40800000,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
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s->dma, serial_hds[i]);
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qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
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qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
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serial_hds[i]);
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s->lcd = pxa2xx_lcdc_init(0x44000000,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
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@ -2195,7 +2202,9 @@ PXA2xxState *pxa270_init(unsigned int sdram_size, const char *revision)
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
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s->i2s = pxa2xx_i2s_init(0x40400000,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), s->dma);
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
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qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
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qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
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s->kp = pxa27x_keypad_init(0x41500000,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_KEYPAD));
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@ -2250,7 +2259,9 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
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exit(1);
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}
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s->mmc = pxa2xx_mmci_init(0x41100000, dinfo->bdrv,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC), s->dma);
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_MMC),
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qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_MMCI),
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qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_MMCI));
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for (i = 0; pxa255_serial[i].io_base; i ++)
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if (serial_hds[i]) {
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@ -2269,7 +2280,9 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
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if (serial_hds[i])
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s->fir = pxa2xx_fir_init(0x40800000,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_ICP),
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s->dma, serial_hds[i]);
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qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_ICP),
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qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_ICP),
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serial_hds[i]);
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s->lcd = pxa2xx_lcdc_init(0x44000000,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_LCD));
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@ -2330,7 +2343,9 @@ PXA2xxState *pxa255_init(unsigned int sdram_size)
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_PWRI2C), 0xff);
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s->i2s = pxa2xx_i2s_init(0x40400000,
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S), s->dma);
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qdev_get_gpio_in(s->pic, PXA2XX_PIC_I2S),
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qdev_get_gpio_in(s->dma, PXA2XX_RX_RQ_I2S),
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qdev_get_gpio_in(s->dma, PXA2XX_TX_RQ_I2S));
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/* GPIO1 resets the processor */
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/* The handler can be overridden by board-specific code */
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186
hw/pxa2xx_dma.c
186
hw/pxa2xx_dma.c
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@ -10,6 +10,12 @@
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#include "hw.h"
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#include "pxa.h"
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#include "sysbus.h"
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#define PXA255_DMA_NUM_CHANNELS 16
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#define PXA27X_DMA_NUM_CHANNELS 32
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#define PXA2XX_DMA_NUM_REQUESTS 75
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typedef struct {
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target_phys_addr_t descr;
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int request;
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} PXA2xxDMAChannel;
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struct PXA2xxDMAState {
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typedef struct PXA2xxDMAState {
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SysBusDevice busdev;
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qemu_irq irq;
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uint32_t stopintr;
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int channels;
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PXA2xxDMAChannel *chan;
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uint8_t *req;
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uint8_t req[PXA2XX_DMA_NUM_REQUESTS];
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/* Flag to avoid recursive DMA invocations. */
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int running;
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};
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#define PXA255_DMA_NUM_CHANNELS 16
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#define PXA27X_DMA_NUM_CHANNELS 32
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#define PXA2XX_DMA_NUM_REQUESTS 75
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} PXA2xxDMAState;
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#define DCSR0 0x0000 /* DMA Control / Status register for Channel 0 */
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#define DCSR31 0x007c /* DMA Control / Status register for Channel 31 */
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pxa2xx_dma_write
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};
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static void pxa2xx_dma_save(QEMUFile *f, void *opaque)
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{
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PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
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int i;
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static void pxa2xx_dma_request(void *opaque, int req_num, int on);
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qemu_put_be32(f, s->channels);
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qemu_put_be32s(f, &s->stopintr);
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qemu_put_be32s(f, &s->eorintr);
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qemu_put_be32s(f, &s->rasintr);
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qemu_put_be32s(f, &s->startintr);
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qemu_put_be32s(f, &s->endintr);
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qemu_put_be32s(f, &s->align);
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qemu_put_be32s(f, &s->pio);
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qemu_put_buffer(f, s->req, PXA2XX_DMA_NUM_REQUESTS);
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for (i = 0; i < s->channels; i ++) {
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qemu_put_betl(f, s->chan[i].descr);
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qemu_put_betl(f, s->chan[i].src);
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qemu_put_betl(f, s->chan[i].dest);
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qemu_put_be32s(f, &s->chan[i].cmd);
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qemu_put_be32s(f, &s->chan[i].state);
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qemu_put_be32(f, s->chan[i].request);
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};
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}
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static int pxa2xx_dma_load(QEMUFile *f, void *opaque, int version_id)
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{
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PXA2xxDMAState *s = (PXA2xxDMAState *) opaque;
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int i;
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if (qemu_get_be32(f) != s->channels)
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return -EINVAL;
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qemu_get_be32s(f, &s->stopintr);
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qemu_get_be32s(f, &s->eorintr);
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qemu_get_be32s(f, &s->rasintr);
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qemu_get_be32s(f, &s->startintr);
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qemu_get_be32s(f, &s->endintr);
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qemu_get_be32s(f, &s->align);
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qemu_get_be32s(f, &s->pio);
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qemu_get_buffer(f, s->req, PXA2XX_DMA_NUM_REQUESTS);
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for (i = 0; i < s->channels; i ++) {
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s->chan[i].descr = qemu_get_betl(f);
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s->chan[i].src = qemu_get_betl(f);
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s->chan[i].dest = qemu_get_betl(f);
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qemu_get_be32s(f, &s->chan[i].cmd);
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qemu_get_be32s(f, &s->chan[i].state);
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s->chan[i].request = qemu_get_be32(f);
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};
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return 0;
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}
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static PXA2xxDMAState *pxa2xx_dma_init(target_phys_addr_t base,
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qemu_irq irq, int channels)
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static int pxa2xx_dma_init(SysBusDevice *dev)
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{
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int i, iomemtype;
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PXA2xxDMAState *s;
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s = (PXA2xxDMAState *)
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qemu_mallocz(sizeof(PXA2xxDMAState));
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s = FROM_SYSBUS(PXA2xxDMAState, dev);
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if (s->channels <= 0) {
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return -1;
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}
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s->channels = channels;
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s->chan = qemu_mallocz(sizeof(PXA2xxDMAChannel) * s->channels);
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s->irq = irq;
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s->req = qemu_mallocz(sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);
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memset(s->chan, 0, sizeof(PXA2xxDMAChannel) * s->channels);
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for (i = 0; i < s->channels; i ++)
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@ -498,29 +446,47 @@ static PXA2xxDMAState *pxa2xx_dma_init(target_phys_addr_t base,
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memset(s->req, 0, sizeof(uint8_t) * PXA2XX_DMA_NUM_REQUESTS);
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qdev_init_gpio_in(&dev->qdev, pxa2xx_dma_request, PXA2XX_DMA_NUM_REQUESTS);
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iomemtype = cpu_register_io_memory(pxa2xx_dma_readfn,
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pxa2xx_dma_writefn, s, DEVICE_NATIVE_ENDIAN);
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cpu_register_physical_memory(base, 0x00010000, iomemtype);
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sysbus_init_mmio(dev, 0x00010000, iomemtype);
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sysbus_init_irq(dev, &s->irq);
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register_savevm(NULL, "pxa2xx_dma", 0, 0, pxa2xx_dma_save, pxa2xx_dma_load, s);
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return s;
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return 0;
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}
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PXA2xxDMAState *pxa27x_dma_init(target_phys_addr_t base,
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qemu_irq irq)
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DeviceState *pxa27x_dma_init(target_phys_addr_t base, qemu_irq irq)
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{
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return pxa2xx_dma_init(base, irq, PXA27X_DMA_NUM_CHANNELS);
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DeviceState *dev;
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dev = qdev_create(NULL, "pxa2xx-dma");
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qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
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qdev_init_nofail(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
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return dev;
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}
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PXA2xxDMAState *pxa255_dma_init(target_phys_addr_t base,
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qemu_irq irq)
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DeviceState *pxa255_dma_init(target_phys_addr_t base, qemu_irq irq)
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{
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return pxa2xx_dma_init(base, irq, PXA255_DMA_NUM_CHANNELS);
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DeviceState *dev;
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dev = qdev_create(NULL, "pxa2xx-dma");
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qdev_prop_set_int32(dev, "channels", PXA27X_DMA_NUM_CHANNELS);
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qdev_init_nofail(dev);
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sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
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sysbus_connect_irq(sysbus_from_qdev(dev), 0, irq);
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return dev;
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}
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void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on)
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static void pxa2xx_dma_request(void *opaque, int req_num, int on)
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{
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PXA2xxDMAState *s = opaque;
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int ch;
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if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS)
|
||||
hw_error("%s: Bad DMA request %i\n", __FUNCTION__, req_num);
|
||||
|
@ -542,3 +508,63 @@ void pxa2xx_dma_request(PXA2xxDMAState *s, int req_num, int on)
|
|||
pxa2xx_dma_update(s, ch);
|
||||
}
|
||||
}
|
||||
|
||||
static bool is_version_0(void *opaque, int version_id)
|
||||
{
|
||||
return version_id == 0;
|
||||
}
|
||||
|
||||
static VMStateDescription vmstate_pxa2xx_dma_chan = {
|
||||
.name = "pxa2xx_dma_chan",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 1,
|
||||
.minimum_version_id_old = 1,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UINTTL(descr, PXA2xxDMAChannel),
|
||||
VMSTATE_UINTTL(src, PXA2xxDMAChannel),
|
||||
VMSTATE_UINTTL(dest, PXA2xxDMAChannel),
|
||||
VMSTATE_UINT32(cmd, PXA2xxDMAChannel),
|
||||
VMSTATE_UINT32(state, PXA2xxDMAChannel),
|
||||
VMSTATE_INT32(request, PXA2xxDMAChannel),
|
||||
VMSTATE_END_OF_LIST(),
|
||||
},
|
||||
};
|
||||
|
||||
static VMStateDescription vmstate_pxa2xx_dma = {
|
||||
.name = "pxa2xx_dma",
|
||||
.version_id = 1,
|
||||
.minimum_version_id = 0,
|
||||
.minimum_version_id_old = 0,
|
||||
.fields = (VMStateField[]) {
|
||||
VMSTATE_UNUSED_TEST(is_version_0, 4),
|
||||
VMSTATE_UINT32(stopintr, PXA2xxDMAState),
|
||||
VMSTATE_UINT32(eorintr, PXA2xxDMAState),
|
||||
VMSTATE_UINT32(rasintr, PXA2xxDMAState),
|
||||
VMSTATE_UINT32(startintr, PXA2xxDMAState),
|
||||
VMSTATE_UINT32(endintr, PXA2xxDMAState),
|
||||
VMSTATE_UINT32(align, PXA2xxDMAState),
|
||||
VMSTATE_UINT32(pio, PXA2xxDMAState),
|
||||
VMSTATE_BUFFER(req, PXA2xxDMAState),
|
||||
VMSTATE_STRUCT_VARRAY_POINTER_INT32(chan, PXA2xxDMAState, channels,
|
||||
vmstate_pxa2xx_dma_chan, PXA2xxDMAChannel),
|
||||
VMSTATE_END_OF_LIST(),
|
||||
},
|
||||
};
|
||||
|
||||
static SysBusDeviceInfo pxa2xx_dma_info = {
|
||||
.init = pxa2xx_dma_init,
|
||||
.qdev.name = "pxa2xx-dma",
|
||||
.qdev.desc = "PXA2xx DMA controller",
|
||||
.qdev.size = sizeof(PXA2xxDMAState),
|
||||
.qdev.vmsd = &vmstate_pxa2xx_dma,
|
||||
.qdev.props = (Property[]) {
|
||||
DEFINE_PROP_INT32("channels", PXA2xxDMAState, channels, -1),
|
||||
DEFINE_PROP_END_OF_LIST(),
|
||||
},
|
||||
};
|
||||
|
||||
static void pxa2xx_dma_register(void)
|
||||
{
|
||||
sysbus_register_withprop(&pxa2xx_dma_info);
|
||||
}
|
||||
device_init(pxa2xx_dma_register);
|
||||
|
|
|
@ -10,10 +10,12 @@
|
|||
#include "hw.h"
|
||||
#include "pxa.h"
|
||||
#include "sd.h"
|
||||
#include "qdev.h"
|
||||
|
||||
struct PXA2xxMMCIState {
|
||||
qemu_irq irq;
|
||||
void *dma;
|
||||
qemu_irq rx_dma;
|
||||
qemu_irq tx_dma;
|
||||
|
||||
SDState *card;
|
||||
|
||||
|
@ -102,10 +104,8 @@ static void pxa2xx_mmci_int_update(PXA2xxMMCIState *s)
|
|||
if (s->cmdat & CMDAT_DMA_EN) {
|
||||
mask |= INT_RXFIFO_REQ | INT_TXFIFO_REQ;
|
||||
|
||||
pxa2xx_dma_request(s->dma,
|
||||
PXA2XX_RX_RQ_MMCI, !!(s->intreq & INT_RXFIFO_REQ));
|
||||
pxa2xx_dma_request(s->dma,
|
||||
PXA2XX_TX_RQ_MMCI, !!(s->intreq & INT_TXFIFO_REQ));
|
||||
qemu_set_irq(s->rx_dma, !!(s->intreq & INT_RXFIFO_REQ));
|
||||
qemu_set_irq(s->tx_dma, !!(s->intreq & INT_TXFIFO_REQ));
|
||||
}
|
||||
|
||||
qemu_set_irq(s->irq, !!(s->intreq & ~mask));
|
||||
|
@ -518,14 +518,16 @@ static int pxa2xx_mmci_load(QEMUFile *f, void *opaque, int version_id)
|
|||
}
|
||||
|
||||
PXA2xxMMCIState *pxa2xx_mmci_init(target_phys_addr_t base,
|
||||
BlockDriverState *bd, qemu_irq irq, void *dma)
|
||||
BlockDriverState *bd, qemu_irq irq,
|
||||
qemu_irq rx_dma, qemu_irq tx_dma)
|
||||
{
|
||||
int iomemtype;
|
||||
PXA2xxMMCIState *s;
|
||||
|
||||
s = (PXA2xxMMCIState *) qemu_mallocz(sizeof(PXA2xxMMCIState));
|
||||
s->irq = irq;
|
||||
s->dma = dma;
|
||||
s->rx_dma = rx_dma;
|
||||
s->tx_dma = tx_dma;
|
||||
|
||||
iomemtype = cpu_register_io_memory(pxa2xx_mmci_readfn,
|
||||
pxa2xx_mmci_writefn, s, DEVICE_NATIVE_ENDIAN);
|
||||
|
|
Loading…
Reference in New Issue