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ppc: Remove stub support for 32-bit hypervisor mode 

a4f30719a8, way back in 2007 noted that "PowerPC hypervisor mode is not
fundamentally available only for PowerPC 64" and added a 32-bit version
of the MSR[HV] bit.

But nothing was ever really done with that; there is no meaningful support
for 32-bit hypervisor mode 13 years later.  Let's stop pretending and just
remove the stubs.

Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
Reviewed-by: Fabiano Rosas <farosas@linux.ibm.com>
Reviewed-by: Greg Kurz <groug@kaod.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
This commit is contained in:
David Gibson 2019-12-11 17:07:44 +11:00
parent f42274cff3
commit 23513f818f
2 changed files with 10 additions and 17 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
target/ppc/cpu.h
View File

@ -24,8 +24,6 @@
#include "exec/cpu-defs.h" #include "exec/cpu-defs.h"
#include "cpu-qom.h" #include "cpu-qom.h"
/* #define PPC_EMULATE_32BITS_HYPV */
#define TCG_GUEST_DEFAULT_MO 0 #define TCG_GUEST_DEFAULT_MO 0
#define TARGET_PAGE_BITS_64K 16 #define TARGET_PAGE_BITS_64K 16
@ -300,13 +298,12 @@ typedef struct ppc_v3_pate_t {
#define MSR_SF 63 /* Sixty-four-bit mode hflags */ #define MSR_SF 63 /* Sixty-four-bit mode hflags */
#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */ #define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */ #define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
#define MSR_SHV 60 /* hypervisor state hflags */ #define MSR_HV 60 /* hypervisor state hflags */
#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */ #define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
#define MSR_TS1 33 #define MSR_TS1 33
#define MSR_TM 32 /* Transactional Memory Available (Book3s) */ #define MSR_TM 32 /* Transactional Memory Available (Book3s) */
#define MSR_CM 31 /* Computation mode for BookE hflags */ #define MSR_CM 31 /* Computation mode for BookE hflags */
#define MSR_ICM 30 /* Interrupt computation mode for BookE */ #define MSR_ICM 30 /* Interrupt computation mode for BookE */
#define MSR_THV 29 /* hypervisor state for 32 bits PowerPC hflags */
#define MSR_GS 28 /* guest state for BookE */ #define MSR_GS 28 /* guest state for BookE */
#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */ #define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
#define MSR_VR 25 /* altivec available x hflags */ #define MSR_VR 25 /* altivec available x hflags */
@ -401,10 +398,13 @@ typedef struct ppc_v3_pate_t {
#define msr_sf ((env->msr >> MSR_SF) & 1) #define msr_sf ((env->msr >> MSR_SF) & 1)
#define msr_isf ((env->msr >> MSR_ISF) & 1) #define msr_isf ((env->msr >> MSR_ISF) & 1)
#define msr_shv ((env->msr >> MSR_SHV) & 1) #if defined(TARGET_PPC64)
#define msr_hv ((env->msr >> MSR_HV) & 1)
#else
#define msr_hv (0)
#endif
#define msr_cm ((env->msr >> MSR_CM) & 1) #define msr_cm ((env->msr >> MSR_CM) & 1)
#define msr_icm ((env->msr >> MSR_ICM) & 1) #define msr_icm ((env->msr >> MSR_ICM) & 1)
#define msr_thv ((env->msr >> MSR_THV) & 1)
#define msr_gs ((env->msr >> MSR_GS) & 1) #define msr_gs ((env->msr >> MSR_GS) & 1)
#define msr_ucle ((env->msr >> MSR_UCLE) & 1) #define msr_ucle ((env->msr >> MSR_UCLE) & 1)
#define msr_vr ((env->msr >> MSR_VR) & 1) #define msr_vr ((env->msr >> MSR_VR) & 1)
@ -449,16 +449,9 @@ typedef struct ppc_v3_pate_t {
/* Hypervisor bit is more specific */ /* Hypervisor bit is more specific */
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
#define MSR_HVB (1ULL << MSR_SHV) #define MSR_HVB (1ULL << MSR_HV)
#define msr_hv msr_shv
#else
#if defined(PPC_EMULATE_32BITS_HYPV)
#define MSR_HVB (1ULL << MSR_THV)
#define msr_hv msr_thv
#else #else
#define MSR_HVB (0ULL) #define MSR_HVB (0ULL)
#define msr_hv (0)
#endif
#endif #endif
/* DSISR */ /* DSISR */

6
target/ppc/translate_init.inc.c
View File

@ -8764,7 +8764,7 @@ POWERPC_FAMILY(POWER8)(ObjectClass *oc, void *data)
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
PPC2_TM | PPC2_PM_ISA206; PPC2_TM | PPC2_PM_ISA206;
pcc->msr_mask = (1ull << MSR_SF) | pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_SHV) | (1ull << MSR_HV) |
(1ull << MSR_TM) | (1ull << MSR_TM) |
(1ull << MSR_VR) | (1ull << MSR_VR) |
(1ull << MSR_VSX) | (1ull << MSR_VSX) |
@ -8976,7 +8976,7 @@ POWERPC_FAMILY(POWER9)(ObjectClass *oc, void *data)
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
pcc->msr_mask = (1ull << MSR_SF) | pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_SHV) | (1ull << MSR_HV) |
(1ull << MSR_TM) | (1ull << MSR_TM) |
(1ull << MSR_VR) | (1ull << MSR_VR) |
(1ull << MSR_VSX) | (1ull << MSR_VSX) |
@ -9186,7 +9186,7 @@ POWERPC_FAMILY(POWER10)(ObjectClass *oc, void *data)
PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 | PPC2_ISA205 | PPC2_ISA207S | PPC2_FP_CVT_S64 |
PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL; PPC2_TM | PPC2_ISA300 | PPC2_PRCNTL;
pcc->msr_mask = (1ull << MSR_SF) | pcc->msr_mask = (1ull << MSR_SF) |
(1ull << MSR_SHV) | (1ull << MSR_HV) |
(1ull << MSR_TM) | (1ull << MSR_TM) |
(1ull << MSR_VR) | (1ull << MSR_VR) |
(1ull << MSR_VSX) | (1ull << MSR_VSX) |