mirror of https://gitee.com/openkylin/qemu.git
target/arm: Implement SVE FP Fast Reduction Group
Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20180627043328.11531-20-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Richard Henderson
Peter Maydell
parent
ca40a6e6e3
commit
23fbe79faa
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@ -725,6 +725,41 @@ DEF_HELPER_FLAGS_5(gvec_rsqrts_s, TCG_CALL_NO_RWG,
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DEF_HELPER_FLAGS_5(gvec_rsqrts_d, TCG_CALL_NO_RWG,
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void, ptr, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_faddv_h, TCG_CALL_NO_RWG,
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i64, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_faddv_s, TCG_CALL_NO_RWG,
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i64, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_faddv_d, TCG_CALL_NO_RWG,
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i64, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_fmaxnmv_h, TCG_CALL_NO_RWG,
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i64, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_fmaxnmv_s, TCG_CALL_NO_RWG,
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i64, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_fmaxnmv_d, TCG_CALL_NO_RWG,
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i64, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_fminnmv_h, TCG_CALL_NO_RWG,
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i64, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_fminnmv_s, TCG_CALL_NO_RWG,
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i64, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_fminnmv_d, TCG_CALL_NO_RWG,
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i64, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_fmaxv_h, TCG_CALL_NO_RWG,
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i64, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_fmaxv_s, TCG_CALL_NO_RWG,
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i64, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_fmaxv_d, TCG_CALL_NO_RWG,
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i64, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_fminv_h, TCG_CALL_NO_RWG,
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i64, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_fminv_s, TCG_CALL_NO_RWG,
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i64, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_4(sve_fminv_d, TCG_CALL_NO_RWG,
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i64, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_fadda_h, TCG_CALL_NO_RWG,
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i64, i64, ptr, ptr, ptr, i32)
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DEF_HELPER_FLAGS_5(sve_fadda_s, TCG_CALL_NO_RWG,
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@ -735,6 +735,14 @@ FMUL_zzx 01100100 0.1 .. rm:3 001000 rn:5 rd:5 \
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FMUL_zzx 01100100 101 index:2 rm:3 001000 rn:5 rd:5 esz=2
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FMUL_zzx 01100100 111 index:1 rm:4 001000 rn:5 rd:5 esz=3
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### SVE FP Fast Reduction Group
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FADDV 01100101 .. 000 000 001 ... ..... ..... @rd_pg_rn
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FMAXNMV 01100101 .. 000 100 001 ... ..... ..... @rd_pg_rn
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FMINNMV 01100101 .. 000 101 001 ... ..... ..... @rd_pg_rn
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FMAXV 01100101 .. 000 110 001 ... ..... ..... @rd_pg_rn
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FMINV 01100101 .. 000 111 001 ... ..... ..... @rd_pg_rn
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### SVE FP Accumulating Reduction Group
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# SVE floating-point serial reduction (predicated)
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@ -2852,6 +2852,67 @@ uint32_t HELPER(sve_while)(void *vd, uint32_t count, uint32_t pred_desc)
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return predtest_ones(d, oprsz, esz_mask);
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}
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/* Recursive reduction on a function;
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* C.f. the ARM ARM function ReducePredicated.
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*
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* While it would be possible to write this without the DATA temporary,
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* it is much simpler to process the predicate register this way.
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* The recursion is bounded to depth 7 (128 fp16 elements), so there's
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* little to gain with a more complex non-recursive form.
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*/
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#define DO_REDUCE(NAME, TYPE, H, FUNC, IDENT) \
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static TYPE NAME##_reduce(TYPE *data, float_status *status, uintptr_t n) \
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{ \
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if (n == 1) { \
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return *data; \
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} else { \
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uintptr_t half = n / 2; \
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TYPE lo = NAME##_reduce(data, status, half); \
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TYPE hi = NAME##_reduce(data + half, status, half); \
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return TYPE##_##FUNC(lo, hi, status); \
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} \
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} \
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uint64_t HELPER(NAME)(void *vn, void *vg, void *vs, uint32_t desc) \
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{ \
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uintptr_t i, oprsz = simd_oprsz(desc), maxsz = simd_maxsz(desc); \
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TYPE data[sizeof(ARMVectorReg) / sizeof(TYPE)]; \
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for (i = 0; i < oprsz; ) { \
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uint16_t pg = *(uint16_t *)(vg + H1_2(i >> 3)); \
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do { \
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TYPE nn = *(TYPE *)(vn + H(i)); \
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*(TYPE *)((void *)data + i) = (pg & 1 ? nn : IDENT); \
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i += sizeof(TYPE), pg >>= sizeof(TYPE); \
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} while (i & 15); \
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} \
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for (; i < maxsz; i += sizeof(TYPE)) { \
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*(TYPE *)((void *)data + i) = IDENT; \
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} \
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return NAME##_reduce(data, vs, maxsz / sizeof(TYPE)); \
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}
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DO_REDUCE(sve_faddv_h, float16, H1_2, add, float16_zero)
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DO_REDUCE(sve_faddv_s, float32, H1_4, add, float32_zero)
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DO_REDUCE(sve_faddv_d, float64, , add, float64_zero)
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/* Identity is floatN_default_nan, without the function call. */
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DO_REDUCE(sve_fminnmv_h, float16, H1_2, minnum, 0x7E00)
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DO_REDUCE(sve_fminnmv_s, float32, H1_4, minnum, 0x7FC00000)
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DO_REDUCE(sve_fminnmv_d, float64, , minnum, 0x7FF8000000000000ULL)
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DO_REDUCE(sve_fmaxnmv_h, float16, H1_2, maxnum, 0x7E00)
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DO_REDUCE(sve_fmaxnmv_s, float32, H1_4, maxnum, 0x7FC00000)
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DO_REDUCE(sve_fmaxnmv_d, float64, , maxnum, 0x7FF8000000000000ULL)
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DO_REDUCE(sve_fminv_h, float16, H1_2, min, float16_infinity)
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DO_REDUCE(sve_fminv_s, float32, H1_4, min, float32_infinity)
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DO_REDUCE(sve_fminv_d, float64, , min, float64_infinity)
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DO_REDUCE(sve_fmaxv_h, float16, H1_2, max, float16_chs(float16_infinity))
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DO_REDUCE(sve_fmaxv_s, float32, H1_4, max, float32_chs(float32_infinity))
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DO_REDUCE(sve_fmaxv_d, float64, , max, float64_chs(float64_infinity))
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#undef DO_REDUCE
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uint64_t HELPER(sve_fadda_h)(uint64_t nn, void *vm, void *vg,
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void *status, uint32_t desc)
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{
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@ -3450,6 +3450,63 @@ static bool trans_FMUL_zzx(DisasContext *s, arg_FMUL_zzx *a, uint32_t insn)
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return true;
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}
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/*
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*** SVE Floating Point Fast Reduction Group
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*/
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typedef void gen_helper_fp_reduce(TCGv_i64, TCGv_ptr, TCGv_ptr,
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TCGv_ptr, TCGv_i32);
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static void do_reduce(DisasContext *s, arg_rpr_esz *a,
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gen_helper_fp_reduce *fn)
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{
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unsigned vsz = vec_full_reg_size(s);
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unsigned p2vsz = pow2ceil(vsz);
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TCGv_i32 t_desc = tcg_const_i32(simd_desc(vsz, p2vsz, 0));
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TCGv_ptr t_zn, t_pg, status;
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TCGv_i64 temp;
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temp = tcg_temp_new_i64();
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t_zn = tcg_temp_new_ptr();
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t_pg = tcg_temp_new_ptr();
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tcg_gen_addi_ptr(t_zn, cpu_env, vec_full_reg_offset(s, a->rn));
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tcg_gen_addi_ptr(t_pg, cpu_env, pred_full_reg_offset(s, a->pg));
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status = get_fpstatus_ptr(a->esz == MO_16);
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fn(temp, t_zn, t_pg, status, t_desc);
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tcg_temp_free_ptr(t_zn);
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tcg_temp_free_ptr(t_pg);
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tcg_temp_free_ptr(status);
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tcg_temp_free_i32(t_desc);
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write_fp_dreg(s, a->rd, temp);
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tcg_temp_free_i64(temp);
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}
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#define DO_VPZ(NAME, name) \
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static bool trans_##NAME(DisasContext *s, arg_rpr_esz *a, uint32_t insn) \
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{ \
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static gen_helper_fp_reduce * const fns[3] = { \
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gen_helper_sve_##name##_h, \
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gen_helper_sve_##name##_s, \
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gen_helper_sve_##name##_d, \
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}; \
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if (a->esz == 0) { \
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return false; \
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} \
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if (sve_access_check(s)) { \
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do_reduce(s, a, fns[a->esz - 1]); \
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} \
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return true; \
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}
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DO_VPZ(FADDV, faddv)
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DO_VPZ(FMINNMV, fminnmv)
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DO_VPZ(FMAXNMV, fmaxnmv)
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DO_VPZ(FMINV, fminv)
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DO_VPZ(FMAXV, fmaxv)
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/*
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*** SVE Floating Point Accumulating Reduction Group
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*/
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