mirror of https://gitee.com/openkylin/qemu.git
Make omap I2C controller work (previously untested). Implement post-OMAP1 changes. Introduce omap L4 abstraction.
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3977 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
balrog
parent
4d3b6f6e12
commit
2988547772
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@ -60,6 +60,10 @@ struct omap_intr_handler_s *omap_inth_init(target_phys_addr_t base,
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unsigned long size, unsigned char nbanks,
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qemu_irq parent_irq, qemu_irq parent_fiq, omap_clk clk);
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struct omap_target_agent_s;
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static inline target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta,
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int region, int iotype) { return 0; }
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/*
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* Common IRQ numbers for level 1 interrupt handler
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* See /usr/include/asm-arm/arch-omap/irqs.h in Linux.
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@ -573,6 +577,8 @@ void omap_mmc_handlers(struct omap_mmc_s *s, qemu_irq ro, qemu_irq cover);
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struct omap_i2c_s;
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struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
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qemu_irq irq, qemu_irq *dma, omap_clk clk);
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struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
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qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk);
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void omap_i2c_reset(struct omap_i2c_s *s);
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i2c_bus *omap_i2c_bus(struct omap_i2c_s *s);
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123
hw/omap_i2c.c
123
hw/omap_i2c.c
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@ -29,6 +29,7 @@ struct omap_i2c_s {
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i2c_slave slave;
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i2c_bus *bus;
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uint8_t revision;
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uint8_t mask;
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uint16_t stat;
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uint16_t dma;
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@ -44,6 +45,9 @@ struct omap_i2c_s {
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uint16_t test;
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};
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#define OMAP2_INTR_REV 0x34
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#define OMAP2_GC_REV 0x34
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static void omap_i2c_interrupts_update(struct omap_i2c_s *s)
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{
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qemu_set_irq(s->irq, s->stat & s->mask);
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@ -124,6 +128,7 @@ static void omap_i2c_fifo_run(struct omap_i2c_s *s)
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i2c_end_transfer(s->bus);
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s->control &= ~(1 << 1); /* STP */
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s->count_cur = s->count;
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s->txlen = 0;
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} else if ((s->control >> 9) & 1) { /* TRX */
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while (ack && s->txlen)
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ack = (i2c_send(s->bus,
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@ -162,6 +167,7 @@ static void omap_i2c_fifo_run(struct omap_i2c_s *s)
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i2c_end_transfer(s->bus);
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s->control &= ~(1 << 1); /* STP */
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s->count_cur = s->count;
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s->txlen = 0;
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} else {
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s->stat |= 1 << 2; /* ARDY */
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s->control &= ~(1 << 10); /* MST */
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@ -201,8 +207,7 @@ static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
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switch (offset) {
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case 0x00: /* I2C_REV */
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/* TODO: set a value greater or equal to real hardware */
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return 0x11; /* REV */
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return s->revision; /* REV */
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case 0x04: /* I2C_IE */
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return s->mask;
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@ -211,12 +216,17 @@ static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
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return s->stat | (i2c_bus_busy(s->bus) << 12);
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case 0x0c: /* I2C_IV */
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if (s->revision >= OMAP2_INTR_REV)
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break;
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ret = ffs(s->stat & s->mask);
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if (ret)
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s->stat ^= 1 << (ret - 1);
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omap_i2c_interrupts_update(s);
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return ret;
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case 0x10: /* I2C_SYSS */
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return (s->control >> 15) & 1; /* I2C_EN */
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case 0x14: /* I2C_BUF */
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return s->dma;
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@ -242,7 +252,7 @@ static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
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} else
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/* XXX: remote access (qualifier) error - what's that? */;
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if (!s->rxlen) {
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s->stat |= ~(1 << 3); /* RRDY */
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s->stat &= ~(1 << 3); /* RRDY */
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if (((s->control >> 10) & 1) && /* MST */
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((~s->control >> 9) & 1)) { /* TRX */
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s->stat |= 1 << 2; /* ARDY */
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@ -254,6 +264,9 @@ static uint32_t omap_i2c_read(void *opaque, target_phys_addr_t addr)
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omap_i2c_interrupts_update(s);
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return ret;
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case 0x20: /* I2C_SYSC */
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return 0;
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case 0x24: /* I2C_CON */
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return s->control;
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@ -293,13 +306,23 @@ static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
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switch (offset) {
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case 0x00: /* I2C_REV */
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case 0x08: /* I2C_STAT */
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case 0x0c: /* I2C_IV */
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OMAP_BAD_REG(addr);
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case 0x10: /* I2C_SYSS */
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OMAP_RO_REG(addr);
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return;
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case 0x04: /* I2C_IE */
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s->mask = value & 0x1f;
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s->mask = value & (s->revision < OMAP2_GC_REV ? 0x1f : 0x3f);
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break;
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case 0x08: /* I2C_STAT */
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if (s->revision < OMAP2_INTR_REV) {
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OMAP_RO_REG(addr);
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return;
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}
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s->stat &= ~(value & 0x3f);
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omap_i2c_interrupts_update(s);
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break;
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case 0x14: /* I2C_BUF */
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@ -335,29 +358,42 @@ static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
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omap_i2c_interrupts_update(s);
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break;
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case 0x20: /* I2C_SYSC */
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if (s->revision < OMAP2_INTR_REV) {
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OMAP_BAD_REG(addr);
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return;
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}
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if (value & 2)
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omap_i2c_reset(s);
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break;
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case 0x24: /* I2C_CON */
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s->control = value & 0xcf07;
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s->control = value & 0xcf87;
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if (~value & (1 << 15)) { /* I2C_EN */
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if (s->revision < OMAP2_INTR_REV)
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omap_i2c_reset(s);
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break;
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}
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if (~value & (1 << 10)) { /* MST */
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if ((value & (1 << 15)) && !(value & (1 << 10))) { /* MST */
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printf("%s: I^2C slave mode not supported\n", __FUNCTION__);
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break;
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}
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if (value & (1 << 9)) { /* XA */
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if ((value & (1 << 15)) && value & (1 << 8)) { /* XA */
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printf("%s: 10-bit addressing mode not supported\n", __FUNCTION__);
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break;
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}
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if (value & (1 << 0)) { /* STT */
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if ((value & (1 << 15)) && value & (1 << 0)) { /* STT */
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nack = !!i2c_start_transfer(s->bus, s->addr[1], /* SA */
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(~value >> 9) & 1); /* TRX */
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s->stat |= nack << 1; /* NACK */
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s->control &= ~(1 << 0); /* STT */
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if (nack)
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s->control &= ~(1 << 1); /* STP */
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else
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else {
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s->count_cur = s->count;
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omap_i2c_fifo_run(s);
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}
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omap_i2c_interrupts_update(s);
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}
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break;
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@ -384,7 +420,12 @@ static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
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break;
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case 0x3c: /* I2C_SYSTEST */
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s->test = value & 0xf00f;
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s->test = value & 0xf80f;
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if (value & (1 << 11)) /* SBB */
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if (s->revision >= OMAP2_INTR_REV) {
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s->stat |= 0x3f;
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omap_i2c_interrupts_update(s);
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}
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if (value & (1 << 15)) /* ST_EN */
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printf("%s: System Test not supported\n", __FUNCTION__);
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break;
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@ -395,6 +436,34 @@ static void omap_i2c_write(void *opaque, target_phys_addr_t addr,
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}
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}
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static void omap_i2c_writeb(void *opaque, target_phys_addr_t addr,
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uint32_t value)
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{
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struct omap_i2c_s *s = (struct omap_i2c_s *) opaque;
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int offset = addr & OMAP_MPUI_REG_MASK;
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switch (offset) {
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case 0x1c: /* I2C_DATA */
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if (s->txlen > 2) {
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/* XXX: remote access (qualifier) error - what's that? */
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break;
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}
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s->fifo <<= 8;
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s->txlen += 1;
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s->fifo |= value & 0xff;
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s->stat &= ~(1 << 10); /* XUDF */
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if (s->txlen > 2)
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s->stat &= ~(1 << 4); /* XRDY */
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omap_i2c_fifo_run(s);
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omap_i2c_interrupts_update(s);
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break;
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default:
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OMAP_BAD_REG(addr);
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return;
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}
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}
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static CPUReadMemoryFunc *omap_i2c_readfn[] = {
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omap_badwidth_read16,
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omap_i2c_read,
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@ -402,9 +471,9 @@ static CPUReadMemoryFunc *omap_i2c_readfn[] = {
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};
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static CPUWriteMemoryFunc *omap_i2c_writefn[] = {
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omap_badwidth_write16,
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omap_i2c_writeb, /* Only the last fifo write can be 8 bit. */
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omap_i2c_write,
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omap_i2c_write, /* TODO: Only the last fifo write can be 8 bit. */
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omap_badwidth_write16,
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};
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struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
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@ -414,6 +483,8 @@ struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
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struct omap_i2c_s *s = (struct omap_i2c_s *)
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qemu_mallocz(sizeof(struct omap_i2c_s));
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/* TODO: set a value greater or equal to real hardware */
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s->revision = 0x11;
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s->base = base;
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s->irq = irq;
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s->drq[0] = dma[0];
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@ -431,6 +502,30 @@ struct omap_i2c_s *omap_i2c_init(target_phys_addr_t base,
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return s;
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}
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struct omap_i2c_s *omap2_i2c_init(struct omap_target_agent_s *ta,
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qemu_irq irq, qemu_irq *dma, omap_clk fclk, omap_clk iclk)
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{
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int iomemtype;
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struct omap_i2c_s *s = (struct omap_i2c_s *)
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qemu_mallocz(sizeof(struct omap_i2c_s));
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s->revision = 0x34;
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s->irq = irq;
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s->drq[0] = dma[0];
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s->drq[1] = dma[1];
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s->slave.event = omap_i2c_event;
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s->slave.recv = omap_i2c_rx;
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s->slave.send = omap_i2c_tx;
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s->bus = i2c_init_bus();
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omap_i2c_reset(s);
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iomemtype = cpu_register_io_memory(0, omap_i2c_readfn,
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omap_i2c_writefn, s);
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s->base = omap_l4_attach(ta, 0, iomemtype);
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return s;
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}
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i2c_bus *omap_i2c_bus(struct omap_i2c_s *s)
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{
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return s->bus;
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