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5K and 20K are Release 1 CPUs. 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3858 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
ths 2007-12-25 17:32:46 +00:00
parent 3aa662faae
commit 29fe0e3490
1 changed files with 3 additions and 3 deletions
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6
target-mips/translate_init.c
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@ -308,7 +308,7 @@ static mips_def_t mips_defs[] =
{ {
.name = "5Kc", .name = "5Kc",
.CP0_PRid = 0x00018100, .CP0_PRid = 0x00018100,
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
(MMU_TYPE_R4000 << CP0C0_MT), (MMU_TYPE_R4000 << CP0C0_MT),
.CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) | .CP0_Config1 = MIPS_CONFIG1 | (31 << CP0C1_MMU) |
(1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
@ -327,7 +327,7 @@ static mips_def_t mips_defs[] =
{ {
.name = "5Kf", .name = "5Kf",
.CP0_PRid = 0x00018100, .CP0_PRid = 0x00018100,
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
(MMU_TYPE_R4000 << CP0C0_MT), (MMU_TYPE_R4000 << CP0C0_MT),
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (31 << CP0C1_MMU) |
(1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) | (1 << CP0C1_IS) | (4 << CP0C1_IL) | (1 << CP0C1_IA) |
@ -351,7 +351,7 @@ static mips_def_t mips_defs[] =
/* We emulate a later version of the 20Kc, earlier ones had a broken /* We emulate a later version of the 20Kc, earlier ones had a broken
WAIT instruction. */ WAIT instruction. */
.CP0_PRid = 0x000182a0, .CP0_PRid = 0x000182a0,
.CP0_Config0 = MIPS_CONFIG0 | (0x1 << CP0C0_AR) | (0x2 << CP0C0_AT) | .CP0_Config0 = MIPS_CONFIG0 | (0x2 << CP0C0_AT) |
(MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI), (MMU_TYPE_R4000 << CP0C0_MT) | (1 << CP0C0_VI),
.CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) | .CP0_Config1 = MIPS_CONFIG1 | (1 << CP0C1_FP) | (47 << CP0C1_MMU) |
(2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) | (2 << CP0C1_IS) | (4 << CP0C1_IL) | (3 << CP0C1_IA) |