mirror of https://gitee.com/openkylin/qemu.git
target-alpha: Implement more CALL_PAL values inline.
In particular, SWPIPL is used quite a lot by the Linux kernel. Doing this inline makes it significantly easier to step through without the debugger getting confused by the mode switch. Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Richard Henderson
Richard Henderson
parent
6a80e088c7
commit
2ace7e55a2
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@ -85,8 +85,10 @@ static TCGv cpu_pc;
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static TCGv cpu_lock_addr;
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static TCGv cpu_lock_st_addr;
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static TCGv cpu_lock_value;
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#ifdef CONFIG_USER_ONLY
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static TCGv cpu_uniq;
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static TCGv cpu_unique;
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#ifndef CONFIG_USER_ONLY
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static TCGv cpu_sysval;
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static TCGv cpu_usp;
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#endif
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/* register names */
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@ -131,9 +133,13 @@ static void alpha_translate_init(void)
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offsetof(CPUState, lock_value),
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"lock_value");
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#ifdef CONFIG_USER_ONLY
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cpu_uniq = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUState, unique), "uniq");
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cpu_unique = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUState, unique), "unique");
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#ifndef CONFIG_USER_ONLY
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cpu_sysval = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUState, sysval), "sysval");
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cpu_usp = tcg_global_mem_new_i64(TCG_AREG0,
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offsetof(CPUState, usp), "usp");
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#endif
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/* register helpers */
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@ -1464,6 +1470,101 @@ static void gen_rx(int ra, int set)
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tcg_temp_free_i32(tmp);
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}
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static ExitStatus gen_call_pal(DisasContext *ctx, int palcode)
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{
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/* We're emulating OSF/1 PALcode. Many of these are trivial access
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to internal cpu registers. */
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/* Unprivileged PAL call */
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if (palcode >= 0x80 && palcode < 0xC0) {
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switch (palcode) {
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case 0x86:
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/* IMB */
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/* No-op inside QEMU. */
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break;
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case 0x9E:
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/* RDUNIQUE */
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tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_unique);
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break;
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case 0x9F:
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/* WRUNIQUE */
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tcg_gen_mov_i64(cpu_unique, cpu_ir[IR_A0]);
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break;
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default:
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return gen_excp(ctx, EXCP_CALL_PAL, palcode & 0xbf);
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}
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return NO_EXIT;
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}
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#ifndef CONFIG_USER_ONLY
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/* Privileged PAL code */
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if (palcode < 0x40 && (ctx->tb->flags & TB_FLAGS_USER_MODE) == 0) {
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switch (palcode) {
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case 0x01:
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/* CFLUSH */
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/* No-op inside QEMU. */
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break;
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case 0x02:
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/* DRAINA */
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/* No-op inside QEMU. */
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break;
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case 0x2D:
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/* WRVPTPTR */
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tcg_gen_st_i64(cpu_ir[IR_A0], cpu_env, offsetof(CPUState, vptptr));
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break;
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case 0x31:
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/* WRVAL */
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tcg_gen_mov_i64(cpu_sysval, cpu_ir[IR_A0]);
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break;
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case 0x32:
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/* RDVAL */
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tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_sysval);
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break;
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case 0x35: {
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/* SWPIPL */
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TCGv tmp;
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/* Note that we already know we're in kernel mode, so we know
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that PS only contains the 3 IPL bits. */
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tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUState, ps));
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/* But make sure and store only the 3 IPL bits from the user. */
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tmp = tcg_temp_new();
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tcg_gen_andi_i64(tmp, cpu_ir[IR_A0], PS_INT_MASK);
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tcg_gen_st8_i64(tmp, cpu_env, offsetof(CPUState, ps));
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tcg_temp_free(tmp);
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break;
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}
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case 0x36:
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/* RDPS */
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tcg_gen_ld8u_i64(cpu_ir[IR_V0], cpu_env, offsetof(CPUState, ps));
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break;
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case 0x38:
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/* WRUSP */
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tcg_gen_mov_i64(cpu_usp, cpu_ir[IR_A0]);
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break;
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case 0x3A:
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/* RDUSP */
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tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_usp);
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break;
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case 0x3C:
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/* WHAMI */
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tcg_gen_ld32s_i64(cpu_ir[IR_V0], cpu_env,
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offsetof(CPUState, cpu_index));
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break;
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default:
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return gen_excp(ctx, EXCP_CALL_PAL, palcode & 0x3f);
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}
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return NO_EXIT;
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}
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#endif
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return gen_invalid(ctx);
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}
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#ifndef CONFIG_USER_ONLY
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#define PR_BYTE 0x100000
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@ -1582,33 +1683,8 @@ static ExitStatus translate_one(DisasContext *ctx, uint32_t insn)
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switch (opc) {
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case 0x00:
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/* CALL_PAL */
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#ifdef CONFIG_USER_ONLY
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if (palcode == 0x9E) {
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/* RDUNIQUE */
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tcg_gen_mov_i64(cpu_ir[IR_V0], cpu_uniq);
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break;
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} else if (palcode == 0x9F) {
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/* WRUNIQUE */
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tcg_gen_mov_i64(cpu_uniq, cpu_ir[IR_A0]);
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break;
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}
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#endif
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if (palcode >= 0x80 && palcode < 0xC0) {
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/* Unprivileged PAL call */
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ret = gen_excp(ctx, EXCP_CALL_PAL, palcode & 0xBF);
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break;
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}
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#ifndef CONFIG_USER_ONLY
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if (palcode < 0x40) {
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/* Privileged PAL code */
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if (ctx->mem_idx != MMU_KERNEL_IDX) {
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goto invalid_opc;
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}
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ret = gen_excp(ctx, EXCP_CALL_PAL, palcode & 0x3F);
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}
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#endif
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/* Invalid PAL call */
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goto invalid_opc;
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ret = gen_call_pal(ctx, palcode);
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break;
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case 0x01:
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/* OPC01 */
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goto invalid_opc;
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