mirror of https://gitee.com/openkylin/qemu.git
target/mips: Clean up handling of CP0 register 12
Clean up handling of CP0 register 12. Reviewed-by: Aleksandar Rikalo <arikalo@wavecomp.com> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com> Message-Id: <1567009614-12438-14-git-send-email-aleksandar.markovic@rt-rk.com>
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@ -350,6 +350,9 @@ typedef struct mips_def_t mips_def_t;
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#define CP0_REG12__STATUS 0
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#define CP0_REG12__INTCTL 1
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#define CP0_REG12__SRSCTL 2
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#define CP0_REG12__SRSMAP 3
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#define CP0_REG12__VIEW_IPL 4
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#define CP0_REG12__SRSMAP2 5
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#define CP0_REG12__GUESTCTL0 6
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#define CP0_REG12__GTOFFSET 7
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/* CP0 Register 13 */
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@ -7177,21 +7177,21 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_12:
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switch (sel) {
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case 0:
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case CP0_REG12__STATUS:
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
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register_name = "Status";
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break;
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case 1:
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case CP0_REG12__INTCTL:
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check_insn(ctx, ISA_MIPS32R2);
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
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register_name = "IntCtl";
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break;
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case 2:
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case CP0_REG12__SRSCTL:
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check_insn(ctx, ISA_MIPS32R2);
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
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register_name = "SRSCtl";
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break;
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case 3:
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case CP0_REG12__SRSMAP:
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check_insn(ctx, ISA_MIPS32R2);
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
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register_name = "SRSMap";
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@ -7893,7 +7893,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_12:
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switch (sel) {
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case 0:
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case CP0_REG12__STATUS:
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save_cpu_state(ctx, 1);
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gen_helper_mtc0_status(cpu_env, arg);
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/* DISAS_STOP isn't good enough here, hflags may have changed. */
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@ -7901,21 +7901,21 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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ctx->base.is_jmp = DISAS_EXIT;
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register_name = "Status";
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break;
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case 1:
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case CP0_REG12__INTCTL:
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check_insn(ctx, ISA_MIPS32R2);
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gen_helper_mtc0_intctl(cpu_env, arg);
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/* Stop translation as we may have switched the execution mode */
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ctx->base.is_jmp = DISAS_STOP;
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register_name = "IntCtl";
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break;
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case 2:
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case CP0_REG12__SRSCTL:
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check_insn(ctx, ISA_MIPS32R2);
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gen_helper_mtc0_srsctl(cpu_env, arg);
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/* Stop translation as we may have switched the execution mode */
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ctx->base.is_jmp = DISAS_STOP;
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register_name = "SRSCtl";
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break;
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case 3:
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case CP0_REG12__SRSMAP:
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check_insn(ctx, ISA_MIPS32R2);
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gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
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/* Stop translation as we may have switched the execution mode */
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@ -8652,21 +8652,21 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_12:
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switch (sel) {
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case 0:
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case CP0_REG12__STATUS:
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Status));
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register_name = "Status";
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break;
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case 1:
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case CP0_REG12__INTCTL:
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check_insn(ctx, ISA_MIPS32R2);
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_IntCtl));
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register_name = "IntCtl";
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break;
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case 2:
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case CP0_REG12__SRSCTL:
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check_insn(ctx, ISA_MIPS32R2);
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSCtl));
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register_name = "SRSCtl";
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break;
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case 3:
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case CP0_REG12__SRSMAP:
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check_insn(ctx, ISA_MIPS32R2);
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gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
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register_name = "SRSMap";
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@ -9356,7 +9356,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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break;
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case CP0_REGISTER_12:
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switch (sel) {
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case 0:
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case CP0_REG12__STATUS:
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save_cpu_state(ctx, 1);
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gen_helper_mtc0_status(cpu_env, arg);
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/* DISAS_STOP isn't good enough here, hflags may have changed. */
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@ -9364,21 +9364,21 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
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ctx->base.is_jmp = DISAS_EXIT;
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register_name = "Status";
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break;
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case 1:
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case CP0_REG12__INTCTL:
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check_insn(ctx, ISA_MIPS32R2);
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gen_helper_mtc0_intctl(cpu_env, arg);
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/* Stop translation as we may have switched the execution mode */
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ctx->base.is_jmp = DISAS_STOP;
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register_name = "IntCtl";
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break;
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case 2:
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case CP0_REG12__SRSCTL:
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check_insn(ctx, ISA_MIPS32R2);
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gen_helper_mtc0_srsctl(cpu_env, arg);
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/* Stop translation as we may have switched the execution mode */
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ctx->base.is_jmp = DISAS_STOP;
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register_name = "SRSCtl";
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break;
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case 3:
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case CP0_REG12__SRSMAP:
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check_insn(ctx, ISA_MIPS32R2);
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gen_mtc0_store32(arg, offsetof(CPUMIPSState, CP0_SRSMap));
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/* Stop translation as we may have switched the execution mode */
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