From 179b9f40f2582de75bd63a11040ae8f7437096b6 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Fri, 3 Oct 2014 16:39:46 -0300 Subject: [PATCH 1/6] pc: Create pc_compat_2_1() functions MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit We will need new compat code for the 2.1 machine-types. Signed-off-by: Eduardo Habkost Signed-off-by: Andreas Färber --- hw/i386/pc_piix.c | 13 ++++++++++++- hw/i386/pc_q35.c | 13 ++++++++++++- 2 files changed, 24 insertions(+), 2 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 1cda5dd068..914337471f 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -302,8 +302,13 @@ static void pc_init_pci(MachineState *machine) pc_init1(machine, 1, 1); } +static void pc_compat_2_1(MachineState *machine) +{ +} + static void pc_compat_2_0(MachineState *machine) { + pc_compat_2_1(machine); /* This value depends on the actual DSDT and SSDT compiled into * the source QEMU; unfortunately it depends on the binary and * not on the machine type, so we cannot make pc-i440fx-1.7 work on @@ -368,6 +373,12 @@ static void pc_compat_1_2(MachineState *machine) x86_cpu_compat_disable_kvm_features(FEAT_KVM, KVM_FEATURE_PV_EOI); } +static void pc_init_pci_2_1(MachineState *machine) +{ + pc_compat_2_1(machine); + pc_init_pci(machine); +} + static void pc_init_pci_2_0(MachineState *machine) { pc_compat_2_0(machine); @@ -471,7 +482,7 @@ static QEMUMachine pc_i440fx_machine_v2_2 = { static QEMUMachine pc_i440fx_machine_v2_1 = { PC_I440FX_2_1_MACHINE_OPTIONS, .name = "pc-i440fx-2.1", - .init = pc_init_pci, + .init = pc_init_pci_2_1, .compat_props = (GlobalProperty[]) { PC_COMPAT_2_1, { /* end of list */ } diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 4d9e3cd69d..bdb1a37769 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -281,8 +281,13 @@ static void pc_q35_init(MachineState *machine) } } +static void pc_compat_2_1(MachineState *machine) +{ +} + static void pc_compat_2_0(MachineState *machine) { + pc_compat_2_1(machine); smbios_legacy_mode = true; has_reserved_memory = false; pc_set_legacy_acpi_data_size(); @@ -316,6 +321,12 @@ static void pc_compat_1_4(MachineState *machine) x86_cpu_compat_set_features("Westmere", FEAT_1_ECX, 0, CPUID_EXT_PCLMULQDQ); } +static void pc_q35_init_2_1(MachineState *machine) +{ + pc_compat_2_1(machine); + pc_q35_init(machine); +} + static void pc_q35_init_2_0(MachineState *machine) { pc_compat_2_0(machine); @@ -368,7 +379,7 @@ static QEMUMachine pc_q35_machine_v2_2 = { static QEMUMachine pc_q35_machine_v2_1 = { PC_Q35_2_1_MACHINE_OPTIONS, .name = "pc-q35-2.1", - .init = pc_q35_init, + .init = pc_q35_init_2_1, .compat_props = (GlobalProperty[]) { PC_COMPAT_2_1, { /* end of list */ } From 1cadaa9482244f7d6477afc34c04a5dad84afdde Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Fri, 3 Oct 2014 16:39:47 -0300 Subject: [PATCH 2/6] target-i386: Rename KVM auto-feature-enable compat function MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The x86_cpu_compat_disable_kvm_features() name was a bit confusing, as it won't forcibly disable the feature for all CPU models (i.e. add it to kvm_default_unset_features), but it will instead turn off the KVM auto-enabling of the feature (i.e. remove it from kvm_default_features), meaning the feature may still be enabled by default in some CPU models). Signed-off-by: Eduardo Habkost Signed-off-by: Andreas Färber --- hw/i386/pc_piix.c | 6 +++--- hw/i386/pc_q35.c | 2 +- target-i386/cpu.c | 2 +- target-i386/cpu.h | 2 +- 4 files changed, 6 insertions(+), 6 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 914337471f..8d63553bc1 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -338,7 +338,7 @@ static void pc_compat_1_7(MachineState *machine) gigabyte_align = false; option_rom_has_mr = true; legacy_acpi_table_size = 6414; - x86_cpu_compat_disable_kvm_features(FEAT_1_ECX, CPUID_EXT_X2APIC); + x86_cpu_compat_kvm_no_autoenable(FEAT_1_ECX, CPUID_EXT_X2APIC); } static void pc_compat_1_6(MachineState *machine) @@ -370,7 +370,7 @@ static void pc_compat_1_3(MachineState *machine) static void pc_compat_1_2(MachineState *machine) { pc_compat_1_3(machine); - x86_cpu_compat_disable_kvm_features(FEAT_KVM, KVM_FEATURE_PV_EOI); + x86_cpu_compat_kvm_no_autoenable(FEAT_KVM, KVM_FEATURE_PV_EOI); } static void pc_init_pci_2_1(MachineState *machine) @@ -441,7 +441,7 @@ static void pc_init_isa(MachineState *machine) if (!machine->cpu_model) { machine->cpu_model = "486"; } - x86_cpu_compat_disable_kvm_features(FEAT_KVM, KVM_FEATURE_PV_EOI); + x86_cpu_compat_kvm_no_autoenable(FEAT_KVM, KVM_FEATURE_PV_EOI); enable_compat_apic_id_mode(); pc_init1(machine, 0, 1); } diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index bdb1a37769..d2484746c3 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -299,7 +299,7 @@ static void pc_compat_1_7(MachineState *machine) smbios_defaults = false; gigabyte_align = false; option_rom_has_mr = true; - x86_cpu_compat_disable_kvm_features(FEAT_1_ECX, CPUID_EXT_X2APIC); + x86_cpu_compat_kvm_no_autoenable(FEAT_1_ECX, CPUID_EXT_X2APIC); } static void pc_compat_1_6(MachineState *machine) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index e4ccee133a..1b25965a64 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -462,7 +462,7 @@ static uint32_t kvm_default_unset_features[FEATURE_WORDS] = { [FEAT_1_ECX] = CPUID_EXT_MONITOR, }; -void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features) +void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features) { kvm_default_features[w] &= ~features; } diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 9f018312b0..a3fc6d86f9 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -1365,7 +1365,7 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access); void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w, uint32_t feat_add, uint32_t feat_remove); -void x86_cpu_compat_disable_kvm_features(FeatureWord w, uint32_t features); +void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features); /* Return name of 32-bit register, from a R_* constant */ From 864867b91b48d38e2bfc7b225197901e6f7d8216 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Fri, 3 Oct 2014 16:39:48 -0300 Subject: [PATCH 3/6] target-i386: Disable CPUID_ACPI by default in KVM mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit KVM never supported the CPUID_ACPI flag, so it doesn't make sense to have it enabled by default when KVM is enabled. The motivation here is exactly the same we had for the MONITOR flag (disabled by commit 136a7e9a85d7047461f8153f7d12c514a3d68f69). And like in the MONITOR flag case, we don't need machine-type compat code because it is currently impossible to run a KVM VM with the ACPI flag set. Signed-off-by: Eduardo Habkost Signed-off-by: Andreas Färber --- target-i386/cpu.c | 1 + 1 file changed, 1 insertion(+) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 1b25965a64..727416ead9 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -459,6 +459,7 @@ static uint32_t kvm_default_features[FEATURE_WORDS] = { /* Features that are not added by default to any CPU model when KVM is enabled. */ static uint32_t kvm_default_unset_features[FEATURE_WORDS] = { + [FEAT_1_EDX] = CPUID_ACPI, [FEAT_1_ECX] = CPUID_EXT_MONITOR, }; From b9fc20bccfcbac082e82896c54862c939d9cb4d2 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Fri, 3 Oct 2014 16:39:49 -0300 Subject: [PATCH 4/6] target-i386: Remove unsupported bits from all CPU models MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit The following CPU features were never supported by neither TCG or KVM, so they are useless on the CPU model definitions, today: * CPUID_DTS (DS) * CPUID_HT * CPUID_TM * CPUID_PBE * CPUID_EXT_DTES64 * CPUID_EXT_DSCPL * CPUID_EXT_EST * CPUID_EXT_TM2 * CPUID_EXT_XTPR * CPUID_EXT_PDCM * CPUID_SVM_LBRV As using "enforce" mode is the only way to ensure guest ABI doesn't change when moving to a different host, we should make "enforce" mode the default or at least encourage management software to always use it. In turn, to make "enforce" usable, we need CPU models that work without always requiring some features to be explicitly disabled. This patch removes the above features from all CPU model definitions. We won't need any machine-type compat code for those changes, because it is impossible to have existing VMs with those features enabled. Signed-off-by: Eduardo Habkost Cc: Aurelien Jarno Signed-off-by: Andreas Färber --- target-i386/cpu.c | 33 ++++++++++++++++++++------------- 1 file changed, 20 insertions(+), 13 deletions(-) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 727416ead9..0c41b929e6 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -679,10 +679,11 @@ static X86CPUDefinition builtin_x86_defs[] = { .family = 16, .model = 2, .stepping = 3, + /* Missing: CPUID_HT */ .features[FEAT_1_EDX] = PPRO_FEATURES | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | - CPUID_PSE36 | CPUID_VME | CPUID_HT, + CPUID_PSE36 | CPUID_VME, .features[FEAT_1_ECX] = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_CX16 | CPUID_EXT_POPCNT, @@ -698,8 +699,9 @@ static X86CPUDefinition builtin_x86_defs[] = { .features[FEAT_8000_0001_ECX] = CPUID_EXT3_LAHF_LM | CPUID_EXT3_SVM | CPUID_EXT3_ABM | CPUID_EXT3_SSE4A, + /* Missing: CPUID_SVM_LBRV */ .features[FEAT_SVM] = - CPUID_SVM_NPT | CPUID_SVM_LBRV, + CPUID_SVM_NPT, .xlevel = 0x8000001A, .model_id = "AMD Phenom(tm) 9550 Quad-Core Processor" }, @@ -710,15 +712,16 @@ static X86CPUDefinition builtin_x86_defs[] = { .family = 6, .model = 15, .stepping = 11, + /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ .features[FEAT_1_EDX] = PPRO_FEATURES | CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | - CPUID_PSE36 | CPUID_VME | CPUID_DTS | CPUID_ACPI | CPUID_SS | - CPUID_HT | CPUID_TM | CPUID_PBE, + CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, + /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, + * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM */ .features[FEAT_1_ECX] = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | - CPUID_EXT_DTES64 | CPUID_EXT_DSCPL | CPUID_EXT_VMX | CPUID_EXT_EST | - CPUID_EXT_TM2 | CPUID_EXT_CX16 | CPUID_EXT_XTPR | CPUID_EXT_PDCM, + CPUID_EXT_VMX | CPUID_EXT_CX16, .features[FEAT_8000_0001_EDX] = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, .features[FEAT_8000_0001_ECX] = @@ -793,13 +796,15 @@ static X86CPUDefinition builtin_x86_defs[] = { .family = 6, .model = 14, .stepping = 8, + /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ .features[FEAT_1_EDX] = PPRO_FEATURES | CPUID_VME | - CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_DTS | CPUID_ACPI | - CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE, + CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | + CPUID_SS, + /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, + * CPUID_EXT_PDCM */ .features[FEAT_1_ECX] = - CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX | - CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_PDCM, + CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX, .features[FEAT_8000_0001_EDX] = CPUID_EXT2_NX, .xlevel = 0x80000008, @@ -872,14 +877,16 @@ static X86CPUDefinition builtin_x86_defs[] = { .family = 6, .model = 28, .stepping = 2, + /* Missing: CPUID_DTS, CPUID_HT, CPUID_TM, CPUID_PBE */ .features[FEAT_1_EDX] = PPRO_FEATURES | - CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | CPUID_DTS | - CPUID_ACPI | CPUID_SS | CPUID_HT | CPUID_TM | CPUID_PBE, + CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_VME | + CPUID_ACPI | CPUID_SS, /* Some CPUs got no CPUID_SEP */ + /* Missing: CPUID_EXT_DSCPL, CPUID_EXT_EST, CPUID_EXT_TM2, + * CPUID_EXT_XTPR */ .features[FEAT_1_ECX] = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | - CPUID_EXT_DSCPL | CPUID_EXT_EST | CPUID_EXT_TM2 | CPUID_EXT_XTPR | CPUID_EXT_MOVBE, .features[FEAT_8000_0001_EDX] = (PPRO_FEATURES & CPUID_EXT2_AMD_ALIASES) | From e93abc147fa628650bdbe7fd57f27462ca40a3c2 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Fri, 3 Oct 2014 16:39:50 -0300 Subject: [PATCH 5/6] target-i386: Don't enable nested VMX by default MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit TCG doesn't support VMX, and nested VMX is not enabled by default in the KVM kernel module. So, there's no reason to have VMX enabled by default on the core2duo and coreduo CPU models, today. Even the newer Intel CPU model definitions don't have it enabled. In this case, we need machine-type compat code, as people may be running the older machine-types on hosts that had VMX nesting enabled. Signed-off-by: Eduardo Habkost Signed-off-by: Andreas Färber --- hw/i386/pc_piix.c | 2 ++ hw/i386/pc_q35.c | 2 ++ target-i386/cpu.c | 8 ++++---- 3 files changed, 8 insertions(+), 4 deletions(-) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 8d63553bc1..751f3e0265 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -304,6 +304,8 @@ static void pc_init_pci(MachineState *machine) static void pc_compat_2_1(MachineState *machine) { + x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, CPUID_EXT_VMX, 0); + x86_cpu_compat_set_features("core2duo", FEAT_1_ECX, CPUID_EXT_VMX, 0); } static void pc_compat_2_0(MachineState *machine) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index d2484746c3..c5ee250954 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -283,6 +283,8 @@ static void pc_q35_init(MachineState *machine) static void pc_compat_2_1(MachineState *machine) { + x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, CPUID_EXT_VMX, 0); + x86_cpu_compat_set_features("core2duo", FEAT_1_ECX, CPUID_EXT_VMX, 0); } static void pc_compat_2_0(MachineState *machine) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 0c41b929e6..b731832077 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -718,10 +718,10 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_PSE36 | CPUID_VME | CPUID_ACPI | CPUID_SS, /* Missing: CPUID_EXT_DTES64, CPUID_EXT_DSCPL, CPUID_EXT_EST, - * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM */ + * CPUID_EXT_TM2, CPUID_EXT_XTPR, CPUID_EXT_PDCM, CPUID_EXT_VMX */ .features[FEAT_1_ECX] = CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_SSSE3 | - CPUID_EXT_VMX | CPUID_EXT_CX16, + CPUID_EXT_CX16, .features[FEAT_8000_0001_EDX] = CPUID_EXT2_LM | CPUID_EXT2_SYSCALL | CPUID_EXT2_NX, .features[FEAT_8000_0001_ECX] = @@ -802,9 +802,9 @@ static X86CPUDefinition builtin_x86_defs[] = { CPUID_MTRR | CPUID_CLFLUSH | CPUID_MCA | CPUID_ACPI | CPUID_SS, /* Missing: CPUID_EXT_EST, CPUID_EXT_TM2 , CPUID_EXT_XTPR, - * CPUID_EXT_PDCM */ + * CPUID_EXT_PDCM, CPUID_EXT_VMX */ .features[FEAT_1_ECX] = - CPUID_EXT_SSE3 | CPUID_EXT_MONITOR | CPUID_EXT_VMX, + CPUID_EXT_SSE3 | CPUID_EXT_MONITOR, .features[FEAT_8000_0001_EDX] = CPUID_EXT2_NX, .xlevel = 0x80000008, From 75d373ef9729bd22fbc46bfd8dcd158cbf6d9777 Mon Sep 17 00:00:00 2001 From: Eduardo Habkost Date: Fri, 3 Oct 2014 16:39:51 -0300 Subject: [PATCH 6/6] target-i386: Disable SVM by default in KVM mode MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Make SVM be disabled by default on all CPU models when in KVM mode. Nested SVM is enabled by default in the KVM kernel module, but it is probably less stable than nested VMX (which is already disabled by default). Add a new compat function, x86_cpu_compat_kvm_no_autodisable(), to keep compatibility on previous machine-types. Suggested-by: Paolo Bonzini Signed-off-by: Eduardo Habkost Signed-off-by: Andreas Färber --- hw/i386/pc_piix.c | 1 + hw/i386/pc_q35.c | 1 + target-i386/cpu.c | 6 ++++++ target-i386/cpu.h | 1 + 4 files changed, 9 insertions(+) diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 751f3e0265..93778cdc8f 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -306,6 +306,7 @@ static void pc_compat_2_1(MachineState *machine) { x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, CPUID_EXT_VMX, 0); x86_cpu_compat_set_features("core2duo", FEAT_1_ECX, CPUID_EXT_VMX, 0); + x86_cpu_compat_kvm_no_autodisable(FEAT_8000_0001_ECX, CPUID_EXT3_SVM); } static void pc_compat_2_0(MachineState *machine) diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index c5ee250954..ec400e16df 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -285,6 +285,7 @@ static void pc_compat_2_1(MachineState *machine) { x86_cpu_compat_set_features("coreduo", FEAT_1_ECX, CPUID_EXT_VMX, 0); x86_cpu_compat_set_features("core2duo", FEAT_1_ECX, CPUID_EXT_VMX, 0); + x86_cpu_compat_kvm_no_autodisable(FEAT_8000_0001_ECX, CPUID_EXT3_SVM); } static void pc_compat_2_0(MachineState *machine) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index b731832077..fa860de55c 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -461,6 +461,7 @@ static uint32_t kvm_default_features[FEATURE_WORDS] = { static uint32_t kvm_default_unset_features[FEATURE_WORDS] = { [FEAT_1_EDX] = CPUID_ACPI, [FEAT_1_ECX] = CPUID_EXT_MONITOR, + [FEAT_8000_0001_ECX] = CPUID_EXT3_SVM, }; void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features) @@ -468,6 +469,11 @@ void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features) kvm_default_features[w] &= ~features; } +void x86_cpu_compat_kvm_no_autodisable(FeatureWord w, uint32_t features) +{ + kvm_default_unset_features[w] &= ~features; +} + /* * Returns the set of feature flags that are supported and migratable by * QEMU, for a given FeatureWord. diff --git a/target-i386/cpu.h b/target-i386/cpu.h index a3fc6d86f9..1b2c12ad94 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -1366,6 +1366,7 @@ void x86_cpu_compat_set_features(const char *cpu_model, FeatureWord w, uint32_t feat_add, uint32_t feat_remove); void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features); +void x86_cpu_compat_kvm_no_autodisable(FeatureWord w, uint32_t features); /* Return name of 32-bit register, from a R_* constant */