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char: rename qemu_chr_write() -> qemu_chr_fe_write() 

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
This commit is contained in:
Anthony Liguori 2011-08-15 11:17:28 -05:00
parent 0bf1dbdcc9
commit 2cc6e0a142
28 changed files with 34 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
gdbstub.c
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@ -382,7 +382,7 @@ static void put_buffer(GDBState *s, const uint8_t *buf, int len)
}
}
#else
qemu_chr_write(s->chr, buf, len);
qemu_chr_fe_write(s->chr, buf, len);
#endif
}

4
hw/ccid-card-passthru.c
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@ -72,8 +72,8 @@ static void ccid_card_vscard_send_msg(PassthruState *s,
scr_msg_header.type = htonl(type);
scr_msg_header.reader_id = htonl(reader_id);
scr_msg_header.length = htonl(length);
qemu_chr_write(s->cs, (uint8_t *)&scr_msg_header, sizeof(VSCMsgHeader));
qemu_chr_write(s->cs, payload, length);
qemu_chr_fe_write(s->cs, (uint8_t *)&scr_msg_header, sizeof(VSCMsgHeader));
qemu_chr_fe_write(s->cs, payload, length);
}
static void ccid_card_vscard_send_apdu(PassthruState *s,

2
hw/debugcon.c
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@ -51,7 +51,7 @@ static void debugcon_ioport_write(void *opaque, uint32_t addr, uint32_t val)
printf("debugcon: write addr=0x%04x val=0x%02x\n", addr, val);
#endif
qemu_chr_write(s->chr, &ch, 1);
qemu_chr_fe_write(s->chr, &ch, 1);
}

2
hw/escc.c
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@ -551,7 +551,7 @@ static void escc_mem_write(void *opaque, target_phys_addr_t addr,
s->tx = val;
if (s->wregs[W_TXCTRL2] & TXCTRL2_TXEN) { // tx enabled
if (s->chr)
qemu_chr_write(s->chr, &s->tx, 1);
qemu_chr_fe_write(s->chr, &s->tx, 1);
else if (s->type == kbd && !s->disabled) {
handle_kbd_command(s, val);
}

2
hw/etraxfs_ser.c
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@ -119,7 +119,7 @@ ser_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
switch (addr)
{
case RW_DOUT:
qemu_chr_write(s->chr, &ch, 1);
qemu_chr_fe_write(s->chr, &ch, 1);
s->regs[R_INTR] |= 3;
s->pending_tx = 1;
s->regs[addr] = value;

2
hw/grlib_apbuart.c
View File

@ -114,7 +114,7 @@ grlib_apbuart_writel(void *opaque, target_phys_addr_t addr, uint32_t value)
switch (addr) {
case DATA_OFFSET:
c = value & 0xFF;
qemu_chr_write(uart->chr, &c, 1);
qemu_chr_fe_write(uart->chr, &c, 1);
return;
case STATUS_OFFSET:

2
hw/lm32_juart.c
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@ -72,7 +72,7 @@ void lm32_juart_set_jtx(DeviceState *d, uint32_t jtx)
s->jtx = jtx;
if (s->chr) {
qemu_chr_write(s->chr, &ch, 1);
qemu_chr_fe_write(s->chr, &ch, 1);
}
}

2
hw/lm32_uart.c
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@ -169,7 +169,7 @@ static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value)
switch (addr) {
case R_RXTX:
if (s->chr) {
qemu_chr_write(s->chr, &ch, 1);
qemu_chr_fe_write(s->chr, &ch, 1);
}
break;
case R_IER:

2
hw/mcf_uart.c
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@ -110,7 +110,7 @@ static void mcf_uart_do_tx(mcf_uart_state *s)
{
if (s->tx_enabled && (s->sr & MCF_UART_TxEMP) == 0) {
if (s->chr)
qemu_chr_write(s->chr, (unsigned char *)&s->tb, 1);
qemu_chr_fe_write(s->chr, (unsigned char *)&s->tb, 1);
s->sr |= MCF_UART_TxEMP;
}
if (s->tx_enabled) {

2
hw/milkymist-uart.c
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@ -77,7 +77,7 @@ static void uart_write(void *opaque, target_phys_addr_t addr, uint32_t value)
switch (addr) {
case R_RXTX:
if (s->chr) {
qemu_chr_write(s->chr, &ch, 1);
qemu_chr_fe_write(s->chr, &ch, 1);
}
trace_milkymist_uart_pulse_irq_tx();
qemu_irq_pulse(s->tx_irq);

6
hw/omap2.c
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@ -748,14 +748,14 @@ static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
if (ch == STI_TRACE_CONTROL_CHANNEL) {
/* Flush channel <i>value</i>. */
qemu_chr_write(s->chr, (const uint8_t *) "\r", 1);
qemu_chr_fe_write(s->chr, (const uint8_t *) "\r", 1);
} else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
if (value == 0xc0 || value == 0xc3) {
/* Open channel <i>ch</i>. */
} else if (value == 0x00)
qemu_chr_write(s->chr, (const uint8_t *) "\n", 1);
qemu_chr_fe_write(s->chr, (const uint8_t *) "\n", 1);
else
qemu_chr_write(s->chr, &byte, 1);
qemu_chr_fe_write(s->chr, &byte, 1);
}
}

2
hw/parallel.c
View File

@ -120,7 +120,7 @@ parallel_ioport_write_sw(void *opaque, uint32_t addr, uint32_t val)
if (val & PARA_CTR_STROBE) {
s->status &= ~PARA_STS_BUSY;
if ((s->control & PARA_CTR_STROBE) == 0)
qemu_chr_write(s->chr, &s->dataw, 1);
qemu_chr_fe_write(s->chr, &s->dataw, 1);
} else {
if (s->control & PARA_CTR_INTEN) {
s->irq_pending = 1;

2
hw/pl011.c
View File

@ -133,7 +133,7 @@ static void pl011_write(void *opaque, target_phys_addr_t offset,
/* ??? Check if transmitter is enabled. */
ch = value;
if (s->chr)
qemu_chr_write(s->chr, &ch, 1);
qemu_chr_fe_write(s->chr, &ch, 1);
s->int_level |= PL011_INT_TX;
pl011_update(s);
break;

2
hw/pxa2xx.c
View File

@ -1923,7 +1923,7 @@ static void pxa2xx_fir_write(void *opaque, target_phys_addr_t addr,
else
ch = ~value;
if (s->chr && s->enable && (s->control[0] & (1 << 3))) /* TXE */
qemu_chr_write(s->chr, &ch, 1);
qemu_chr_fe_write(s->chr, &ch, 1);
break;
case ICSR0:
s->status[0] &= ~(value & 0x66);

2
hw/serial.c
View File

@ -334,7 +334,7 @@ static void serial_xmit(void *opaque)
if (s->mcr & UART_MCR_LOOP) {
/* in loopback mode, say that we just received a char */
serial_receive1(s, &s->tsr, 1);
} else if (qemu_chr_write(s->chr, &s->tsr, 1) != 1) {
} else if (qemu_chr_fe_write(s->chr, &s->tsr, 1) != 1) {
if ((s->tsr_retry > 0) && (s->tsr_retry <= MAX_XMIT_RETRY)) {
s->tsr_retry++;
qemu_mod_timer(s->transmit_timer, new_xmit_ts + s->char_transmit_time);

2
hw/sh_serial.c
View File

@ -105,7 +105,7 @@ static void sh_serial_write(void *opaque, uint32_t offs, uint32_t val)
case 0x0c: /* FTDR / TDR */
if (s->chr) {
ch = val;
qemu_chr_write(s->chr, &ch, 1);
qemu_chr_fe_write(s->chr, &ch, 1);
}
s->dr = val;
s->flags &= ~SH_SERIAL_FLAG_TDE;

4
hw/spapr_vty.c
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@ -50,8 +50,8 @@ void vty_putchars(VIOsPAPRDevice *sdev, uint8_t *buf, int len)
{
VIOsPAPRVTYDevice *dev = (VIOsPAPRVTYDevice *)sdev;
/* FIXME: should check the qemu_chr_write() return value */
qemu_chr_write(dev->chardev, buf, len);
/* FIXME: should check the qemu_chr_fe_write() return value */
qemu_chr_fe_write(dev->chardev, buf, len);
}
static int spapr_vty_init(VIOsPAPRDevice *sdev)

2
hw/strongarm.c
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@ -1067,7 +1067,7 @@ static void strongarm_uart_tx(void *opaque)
if (s->utcr3 & UTCR3_LBM) /* loopback */ {
strongarm_uart_receive(s, &s->tx_fifo[s->tx_start], 1);
} else if (s->chr) {
qemu_chr_write(s->chr, &s->tx_fifo[s->tx_start], 1);
qemu_chr_fe_write(s->chr, &s->tx_fifo[s->tx_start], 1);
}
s->tx_start = (s->tx_start + 1) % 8;

4
hw/syborg_serial.c
View File

@ -119,7 +119,7 @@ static void do_dma_tx(SyborgSerialState *s, uint32_t count)
/* optimize later. Now, 1 byte per iteration */
while (count--) {
cpu_physical_memory_read(s->dma_tx_ptr, &ch, 1);
qemu_chr_write(s->chr, &ch, 1);
qemu_chr_fe_write(s->chr, &ch, 1);
s->dma_tx_ptr++;
}
} else {
@ -203,7 +203,7 @@ static void syborg_serial_write(void *opaque, target_phys_addr_t offset,
case SERIAL_DATA:
ch = value;
if (s->chr)
qemu_chr_write(s->chr, &ch, 1);
qemu_chr_fe_write(s->chr, &ch, 1);
break;
case SERIAL_INT_ENABLE:
s->int_enable = value;

2
hw/usb-serial.c
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@ -371,7 +371,7 @@ static int usb_serial_handle_data(USBDevice *dev, USBPacket *p)
goto fail;
for (i = 0; i < p->iov.niov; i++) {
iov = p->iov.iov + i;
qemu_chr_write(s->cs, iov->iov_base, iov->iov_len);
qemu_chr_fe_write(s->cs, iov->iov_base, iov->iov_len);
}
break;

2
hw/virtio-console.c
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@ -27,7 +27,7 @@ static ssize_t flush_buf(VirtIOSerialPort *port, const uint8_t *buf, size_t len)
VirtConsole *vcon = DO_UPCAST(VirtConsole, port, port);
ssize_t ret;
ret = qemu_chr_write(vcon->chr, buf, len);
ret = qemu_chr_fe_write(vcon->chr, buf, len);
trace_virtio_console_flush_buf(port->id, len, ret);
if (ret < 0) {

2
hw/xen_console.c
View File

@ -156,7 +156,7 @@ static void xencons_send(struct XenConsole *con)
size = con->buffer.size - con->buffer.consumed;
if (con->chr)
len = qemu_chr_write(con->chr, con->buffer.data + con->buffer.consumed,
len = qemu_chr_fe_write(con->chr, con->buffer.data + con->buffer.consumed,
size);
else
len = size;

2
hw/xilinx_uartlite.c
View File

@ -129,7 +129,7 @@ uart_writel (void *opaque, target_phys_addr_t addr, uint32_t value)
case R_TX:
if (s->chr)
qemu_chr_write(s->chr, &ch, 1);
qemu_chr_fe_write(s->chr, &ch, 1);
s->regs[addr] = value;

2
monitor.c
View File

@ -247,7 +247,7 @@ static int monitor_read_password(Monitor *mon, ReadLineFunc *readline_func,
void monitor_flush(Monitor *mon)
{
if (mon && mon->outbuf_index != 0 && !mon->mux_out) {
qemu_chr_write(mon->chr, mon->outbuf, mon->outbuf_index);
qemu_chr_fe_write(mon->chr, mon->outbuf, mon->outbuf_index);
mon->outbuf_index = 0;
}
}

4
qemu-char.c
View File

@ -139,7 +139,7 @@ void qemu_chr_generic_open(CharDriverState *s)
}
}
int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len)
int qemu_chr_fe_write(CharDriverState *s, const uint8_t *buf, int len)
{
return s->chr_write(s, buf, len);
}
@ -185,7 +185,7 @@ void qemu_chr_printf(CharDriverState *s, const char *fmt, ...)
va_list ap;
va_start(ap, fmt);
vsnprintf(buf, sizeof(buf), fmt, ap);
qemu_chr_write(s, (uint8_t *)buf, strlen(buf));
qemu_chr_fe_write(s, (uint8_t *)buf, strlen(buf));
va_end(ap);
}

2
qemu-char.h
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@ -87,7 +87,7 @@ void qemu_chr_guest_close(struct CharDriverState *chr);
void qemu_chr_close(CharDriverState *chr);
void qemu_chr_printf(CharDriverState *s, const char *fmt, ...)
GCC_FMT_ATTR(2, 3);
int qemu_chr_write(CharDriverState *s, const uint8_t *buf, int len);
int qemu_chr_fe_write(CharDriverState *s, const uint8_t *buf, int len);
void qemu_chr_send_event(CharDriverState *s, int event);
void qemu_chr_add_handlers(CharDriverState *s,
IOCanReadHandler *fd_can_read,

2
slirp/slirp.c
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@ -818,7 +818,7 @@ int slirp_add_exec(Slirp *slirp, int do_pty, const void *args,
ssize_t slirp_send(struct socket *so, const void *buf, size_t len, int flags)
{
if (so->s == -1 && so->extra) {
qemu_chr_write(so->extra, buf, len);
qemu_chr_fe_write(so->extra, buf, len);
return len;
}

2
usb-redir.c
View File

@ -225,7 +225,7 @@ static int usbredir_write(void *priv, uint8_t *data, int count)
{
USBRedirDevice *dev = priv;
return qemu_chr_write(dev->cs, data, count);
return qemu_chr_fe_write(dev->cs, data, count);
}
/*