mirror of https://gitee.com/openkylin/qemu.git
target-ppc: Fix booke206 tlbwe TLB instruction
When overwritting a valid TLB entry with a new one, the previous page were not flushed in QEMU TLB, leading to incoherent mapping. This commit fixes this. Signed-off-by: Luc MICHEL <luc.michel@git.antfield.fr> Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
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@ -2570,6 +2570,17 @@ void helper_booke_setpid(CPUPPCState *env, uint32_t pidn, target_ulong pid)
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tlb_flush(CPU(cpu));
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}
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static inline void flush_page(CPUPPCState *env, ppcmas_tlb_t *tlb)
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{
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PowerPCCPU *cpu = ppc_env_get_cpu(env);
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if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {
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tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK);
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} else {
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tlb_flush(CPU(cpu));
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}
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}
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void helper_booke206_tlbwe(CPUPPCState *env)
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{
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PowerPCCPU *cpu = ppc_env_get_cpu(env);
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@ -2628,6 +2639,21 @@ void helper_booke206_tlbwe(CPUPPCState *env)
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if (msr_gs) {
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cpu_abort(CPU(cpu), "missing HV implementation\n");
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}
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if (tlb->mas1 & MAS1_VALID) {
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/* Invalidate the page in QEMU TLB if it was a valid entry.
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*
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* In "PowerPC e500 Core Family Reference Manual, Rev. 1",
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* Section "12.4.2 TLB Write Entry (tlbwe) Instruction":
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* (https://www.nxp.com/docs/en/reference-manual/E500CORERM.pdf)
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*
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* "Note that when an L2 TLB entry is written, it may be displacing an
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* already valid entry in the same L2 TLB location (a victim). If a
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* valid L1 TLB entry corresponds to the L2 MMU victim entry, that L1
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* TLB entry is automatically invalidated." */
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flush_page(env, tlb);
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}
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tlb->mas7_3 = ((uint64_t)env->spr[SPR_BOOKE_MAS7] << 32) |
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env->spr[SPR_BOOKE_MAS3];
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tlb->mas1 = env->spr[SPR_BOOKE_MAS1];
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@ -2663,11 +2689,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
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tlb->mas1 &= ~MAS1_IPROT;
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}
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if (booke206_tlb_to_page_size(env, tlb) == TARGET_PAGE_SIZE) {
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tlb_flush_page(CPU(cpu), tlb->mas2 & MAS2_EPN_MASK);
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} else {
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tlb_flush(CPU(cpu));
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}
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flush_page(env, tlb);
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}
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static inline void booke206_tlb_to_mas(CPUPPCState *env, ppcmas_tlb_t *tlb)
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