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hw/c*: pass owner to memory_region_init* functions 

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Paolo Bonzini 2013-06-06 21:25:08 -04:00
parent 2d256e6f65
commit 300b1fc68c
19 changed files with 36 additions and 29 deletions
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2
hw/char/cadence_uart.c
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@ -442,7 +442,7 @@ static int cadence_uart_init(SysBusDevice *dev)
{
UartState *s = FROM_SYSBUS(UartState, dev);
memory_region_init_io(&s->iomem, NULL, &uart_ops, s, "uart", 0x1000);
memory_region_init_io(&s->iomem, OBJECT(s), &uart_ops, s, "uart", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);

2
hw/char/debugcon.c
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@ -103,7 +103,7 @@ static void debugcon_isa_realizefn(DeviceState *dev, Error **errp)
error_propagate(errp, err);
return;
}
memory_region_init_io(&s->io, NULL, &debugcon_ops, s,
memory_region_init_io(&s->io, OBJECT(dev), &debugcon_ops, s,
TYPE_ISA_DEBUGCON_DEVICE, 1);
memory_region_add_subregion(isa_address_space_io(d),
isa->iobase, &s->io);

2
hw/char/escc.c
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@ -886,7 +886,7 @@ static int escc_init1(SysBusDevice *dev)
s->chn[0].otherchn = &s->chn[1];
s->chn[1].otherchn = &s->chn[0];
memory_region_init_io(&s->mmio, NULL, &escc_mem_ops, s, "escc",
memory_region_init_io(&s->mmio, OBJECT(s), &escc_mem_ops, s, "escc",
ESCC_SIZE << s->it_shift);
sysbus_init_mmio(dev, &s->mmio);

3
hw/char/etraxfs_ser.c
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@ -211,7 +211,8 @@ static int etraxfs_ser_init(SysBusDevice *dev)
struct etrax_serial *s = FROM_SYSBUS(typeof (*s), dev);
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->mmio, NULL, &ser_ops, s, "etraxfs-serial", R_MAX * 4);
memory_region_init_io(&s->mmio, OBJECT(s), &ser_ops, s,
"etraxfs-serial", R_MAX * 4);
sysbus_init_mmio(dev, &s->mmio);
s->chr = qemu_char_get_next_serial();

4
hw/char/exynos4210_uart.c
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@ -630,8 +630,8 @@ static int exynos4210_uart_init(SysBusDevice *dev)
Exynos4210UartState *s = FROM_SYSBUS(Exynos4210UartState, dev);
/* memory mapping */
memory_region_init_io(&s->iomem, NULL, &exynos4210_uart_ops, s, "exynos4210.uart",
EXYNOS4210_UART_REGS_MEM_SIZE);
memory_region_init_io(&s->iomem, OBJECT(s), &exynos4210_uart_ops, s,
"exynos4210.uart", EXYNOS4210_UART_REGS_MEM_SIZE);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);

2
hw/char/grlib_apbuart.c
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@ -242,7 +242,7 @@ static int grlib_apbuart_init(SysBusDevice *dev)
sysbus_init_irq(dev, &uart->irq);
memory_region_init_io(&uart->iomem, NULL, &grlib_apbuart_ops, uart,
memory_region_init_io(&uart->iomem, OBJECT(uart), &grlib_apbuart_ops, uart,
"uart", UART_REG_SIZE);
sysbus_init_mmio(dev, &uart->iomem);

3
hw/char/imx_serial.c
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@ -386,7 +386,8 @@ static int imx_serial_init(SysBusDevice *dev)
IMXSerialState *s = FROM_SYSBUS(IMXSerialState, dev);
memory_region_init_io(&s->iomem, NULL, &imx_serial_ops, s, "imx-serial", 0x1000);
memory_region_init_io(&s->iomem, OBJECT(s), &imx_serial_ops, s,
"imx-serial", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);

3
hw/char/lm32_uart.c
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@ -250,7 +250,8 @@ static int lm32_uart_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->iomem, NULL, &uart_ops, s, "uart", R_MAX * 4);
memory_region_init_io(&s->iomem, OBJECT(s), &uart_ops, s,
"uart", R_MAX * 4);
sysbus_init_mmio(dev, &s->iomem);
s->chr = qemu_char_get_next_serial();

2
hw/char/milkymist-uart.c
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@ -196,7 +196,7 @@ static int milkymist_uart_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
memory_region_init_io(&s->regs_region, NULL, &uart_mmio_ops, s,
memory_region_init_io(&s->regs_region, OBJECT(s), &uart_mmio_ops, s,
"milkymist-uart", R_MAX * 4);
sysbus_init_mmio(dev, &s->regs_region);

2
hw/char/pl011.c
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@ -265,7 +265,7 @@ static int pl011_init(SysBusDevice *dev, const unsigned char *id)
{
pl011_state *s = FROM_SYSBUS(pl011_state, dev);
memory_region_init_io(&s->iomem, NULL, &pl011_ops, s, "pl011", 0x1000);
memory_region_init_io(&s->iomem, OBJECT(s), &pl011_ops, s, "pl011", 0x1000);
sysbus_init_mmio(dev, &s->iomem);
sysbus_init_irq(dev, &s->irq);
s->id = id;

2
hw/char/serial-isa.c
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@ -72,7 +72,7 @@ static void serial_isa_realizefn(DeviceState *dev, Error **errp)
serial_realize_core(s, errp);
qdev_set_legacy_instance_id(dev, isa->iobase, 3);
memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8);
memory_region_init_io(&s->io, OBJECT(isa), &serial_io_ops, s, "serial", 8);
isa_register_ioport(isadev, &s->io, isa->iobase);
}

7
hw/char/serial-pci.c
View File

@ -63,7 +63,7 @@ static int serial_pci_init(PCIDevice *dev)
pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
s->irq = pci->dev.irq[0];
memory_region_init_io(&s->io, NULL, &serial_io_ops, s, "serial", 8);
memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s, "serial", 8);
pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &s->io);
return 0;
}
@ -102,7 +102,7 @@ static int multi_serial_pci_init(PCIDevice *dev)
assert(pci->ports <= PCI_SERIAL_MAX_PORTS);
pci->dev.config[PCI_INTERRUPT_PIN] = 0x01;
memory_region_init(&pci->iobar, NULL, "multiserial", 8 * pci->ports);
memory_region_init(&pci->iobar, OBJECT(pci), "multiserial", 8 * pci->ports);
pci_register_bar(&pci->dev, 0, PCI_BASE_ADDRESS_SPACE_IO, &pci->iobar);
pci->irqs = qemu_allocate_irqs(multi_serial_irq_mux, pci,
pci->ports);
@ -118,7 +118,8 @@ static int multi_serial_pci_init(PCIDevice *dev)
}
s->irq = pci->irqs[i];
pci->name[i] = g_strdup_printf("uart #%d", i+1);
memory_region_init_io(&s->io, NULL, &serial_io_ops, s, pci->name[i], 8);
memory_region_init_io(&s->io, OBJECT(pci), &serial_io_ops, s,
pci->name[i], 8);
memory_region_add_subregion(&pci->iobar, 8 * i, &s->io);
}
return 0;

12
hw/char/tpci200.c
View File

@ -588,17 +588,17 @@ static int tpci200_initfn(PCIDevice *pci_dev)
pci_set_long(c + 0x48, 0x00024C06);
pci_set_long(c + 0x4C, 0x00000003);
memory_region_init_io(&s->mmio, NULL, &tpci200_cfg_ops,
memory_region_init_io(&s->mmio, OBJECT(s), &tpci200_cfg_ops,
s, "tpci200_mmio", 128);
memory_region_init_io(&s->io, NULL, &tpci200_cfg_ops,
memory_region_init_io(&s->io, OBJECT(s), &tpci200_cfg_ops,
s, "tpci200_io", 128);
memory_region_init_io(&s->las0, NULL, &tpci200_las0_ops,
memory_region_init_io(&s->las0, OBJECT(s), &tpci200_las0_ops,
s, "tpci200_las0", 256);
memory_region_init_io(&s->las1, NULL, &tpci200_las1_ops,
memory_region_init_io(&s->las1, OBJECT(s), &tpci200_las1_ops,
s, "tpci200_las1", 1024);
memory_region_init_io(&s->las2, NULL, &tpci200_las2_ops,
memory_region_init_io(&s->las2, OBJECT(s), &tpci200_las2_ops,
s, "tpci200_las2", 1024*1024*32);
memory_region_init_io(&s->las3, NULL, &tpci200_las3_ops,
memory_region_init_io(&s->las3, OBJECT(s), &tpci200_las3_ops,
s, "tpci200_las3", 1024*1024*16);
pci_register_bar(&s->dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->mmio);
pci_register_bar(&s->dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->io);

4
hw/char/xilinx_uartlite.c
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@ -199,8 +199,8 @@ static int xilinx_uartlite_init(SysBusDevice *dev)
sysbus_init_irq(dev, &s->irq);
uart_update_status(s);
memory_region_init_io(&s->mmio, NULL, &uart_ops, s, "xlnx.xps-uartlite",
R_MAX * 4);
memory_region_init_io(&s->mmio, OBJECT(s), &uart_ops, s,
"xlnx.xps-uartlite", R_MAX * 4);
sysbus_init_mmio(dev, &s->mmio);
s->chr = qemu_char_get_next_serial();

2
hw/core/empty_slot.c
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@ -70,7 +70,7 @@ static int empty_slot_init1(SysBusDevice *dev)
{
EmptySlot *s = FROM_SYSBUS(EmptySlot, dev);
memory_region_init_io(&s->iomem, NULL, &empty_slot_ops, s,
memory_region_init_io(&s->iomem, OBJECT(s), &empty_slot_ops, s,
"empty-slot", s->size);
sysbus_init_mmio(dev, &s->iomem);
return 0;

3
hw/cpu/a15mpcore.c
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@ -68,7 +68,8 @@ static int a15mp_priv_init(SysBusDevice *dev)
* 0x5000-0x5fff -- GIC virtual interface control (not modelled)
* 0x6000-0x7fff -- GIC virtual CPU interface (not modelled)
*/
memory_region_init(&s->container, NULL, "a15mp-priv-container", 0x8000);
memory_region_init(&s->container, OBJECT(s),
"a15mp-priv-container", 0x8000);
memory_region_add_subregion(&s->container, 0x1000,
sysbus_mmio_get_region(busdev, 0));
memory_region_add_subregion(&s->container, 0x2000,

2
hw/cpu/a9mpcore.c
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@ -71,7 +71,7 @@ static int a9mp_priv_init(SysBusDevice *dev)
*
* We should implement the global timer but don't currently do so.
*/
memory_region_init(&s->container, NULL, "a9mp-priv-container", 0x2000);
memory_region_init(&s->container, OBJECT(s), "a9mp-priv-container", 0x2000);
memory_region_add_subregion(&s->container, 0,
sysbus_mmio_get_region(scubusdev, 0));
/* GIC CPU interface */

6
hw/cpu/arm11mpcore.c
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@ -87,8 +87,10 @@ static void mpcore_priv_map_setup(ARM11MPCorePriveState *s)
SysBusDevice *gicbusdev = SYS_BUS_DEVICE(s->gic);
SysBusDevice *timerbusdev = SYS_BUS_DEVICE(s->mptimer);
SysBusDevice *wdtbusdev = SYS_BUS_DEVICE(s->wdtimer);
memory_region_init(&s->container, NULL, "mpcode-priv-container", 0x2000);
memory_region_init_io(&s->iomem, NULL, &mpcore_scu_ops, s, "mpcore-scu", 0x100);
memory_region_init(&s->container, OBJECT(s),
"mpcode-priv-container", 0x2000);
memory_region_init_io(&s->iomem, OBJECT(s),
&mpcore_scu_ops, s, "mpcore-scu", 0x100);
memory_region_add_subregion(&s->container, 0, &s->iomem);
/* GIC CPU interfaces: "current CPU" at 0x100, then specific CPUs
* at 0x200, 0x300...

2
hw/cpu/icc_bus.c
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@ -95,7 +95,7 @@ static void icc_bridge_init(Object *obj)
/* Do not change order of registering regions,
* APIC must be first registered region, board maps it by 0 index
*/
memory_region_init(&s->apic_container, NULL, "icc-apic-container",
memory_region_init(&s->apic_container, obj, "icc-apic-container",
APIC_SPACE_SIZE);
sysbus_init_mmio(sb, &s->apic_container);
s->icc_bus.apic_address_space = &s->apic_container;