mirror of https://gitee.com/openkylin/qemu.git
target-arm: convert rest of disas_arm_insn / disas_thumb2_insn not to use cpu_T
Signed-off-by: Filip Navara <filip.navara@gmail.com> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Filip Navara
Aurelien Jarno
parent
396e467cb1
commit
3174f8e91f
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@ -6444,10 +6444,10 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
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ARCH(6K);
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else
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ARCH(6);
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gen_movl_T1_reg(s, rn);
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addr = cpu_T[1];
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addr = tcg_temp_local_new_i32();
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tcg_gen_mov_i32(addr, cpu_R[rn]);
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if (insn & (1 << 20)) {
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gen_helper_mark_exclusive(cpu_env, cpu_T[1]);
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gen_helper_mark_exclusive(cpu_env, addr);
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switch (op1) {
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case 0: /* ldrex */
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tmp = gen_ld32(addr, IS_USER(s));
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@ -6472,9 +6472,9 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
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} else {
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int label = gen_new_label();
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rm = insn & 0xf;
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gen_helper_test_exclusive(cpu_T[0], cpu_env, addr);
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tcg_gen_brcondi_i32(TCG_COND_NE, cpu_T[0],
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0, label);
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tmp2 = tcg_temp_local_new_i32();
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gen_helper_test_exclusive(tmp2, cpu_env, addr);
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tcg_gen_brcondi_i32(TCG_COND_NE, tmp2, 0, label);
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tmp = load_reg(s,rm);
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switch (op1) {
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case 0: /* strex */
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@ -6496,8 +6496,10 @@ static void disas_arm_insn(CPUState * env, DisasContext *s)
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abort();
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}
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gen_set_label(label);
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gen_movl_reg_T0(s, rd);
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tcg_gen_mov_i32(cpu_R[rd], tmp2);
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tcg_temp_free(tmp2);
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}
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tcg_temp_free(addr);
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} else {
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/* SWP instruction */
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rm = (insn) & 0xf;
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@ -7238,22 +7240,24 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
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}
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} else if ((insn & (1 << 23)) == 0) {
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/* Load/store exclusive word. */
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gen_movl_T1_reg(s, rn);
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addr = cpu_T[1];
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addr = tcg_temp_local_new();
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tcg_gen_mov_i32(addr, cpu_R[rn]);
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if (insn & (1 << 20)) {
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gen_helper_mark_exclusive(cpu_env, cpu_T[1]);
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gen_helper_mark_exclusive(cpu_env, addr);
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tmp = gen_ld32(addr, IS_USER(s));
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store_reg(s, rd, tmp);
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} else {
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int label = gen_new_label();
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gen_helper_test_exclusive(cpu_T[0], cpu_env, addr);
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tcg_gen_brcondi_i32(TCG_COND_NE, cpu_T[0],
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0, label);
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tmp2 = tcg_temp_local_new();
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gen_helper_test_exclusive(tmp2, cpu_env, addr);
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tcg_gen_brcondi_i32(TCG_COND_NE, tmp2, 0, label);
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tmp = load_reg(s, rs);
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gen_st32(tmp, cpu_T[1], IS_USER(s));
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gen_st32(tmp, addr, IS_USER(s));
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gen_set_label(label);
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gen_movl_reg_T0(s, rd);
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tcg_gen_mov_i32(cpu_R[rd], tmp2);
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tcg_temp_free(tmp2);
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}
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tcg_temp_free(addr);
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} else if ((insn & (1 << 6)) == 0) {
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/* Table Branch. */
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if (rn == 15) {
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@ -7283,10 +7287,8 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
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we never have multiple CPUs running in parallel,
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so it is good enough. */
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op = (insn >> 4) & 0x3;
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/* Must use a global reg for the address because we have
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a conditional branch in the store instruction. */
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gen_movl_T1_reg(s, rn);
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addr = cpu_T[1];
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addr = tcg_temp_local_new();
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tcg_gen_mov_i32(addr, cpu_R[rn]);
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if (insn & (1 << 20)) {
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gen_helper_mark_exclusive(cpu_env, addr);
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switch (op) {
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@ -7308,9 +7310,9 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
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store_reg(s, rs, tmp);
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} else {
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int label = gen_new_label();
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/* Must use a global that is not killed by the branch. */
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gen_helper_test_exclusive(cpu_T[0], cpu_env, addr);
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tcg_gen_brcondi_i32(TCG_COND_NE, cpu_T[0], 0, label);
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tmp2 = tcg_temp_local_new();
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gen_helper_test_exclusive(tmp2, cpu_env, addr);
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tcg_gen_brcondi_i32(TCG_COND_NE, tmp2, 0, label);
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tmp = load_reg(s, rs);
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switch (op) {
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case 0:
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@ -7329,8 +7331,10 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
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goto illegal_op;
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}
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gen_set_label(label);
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gen_movl_reg_T0(s, rm);
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tcg_gen_mov_i32(cpu_R[rm], tmp2);
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tcg_temp_free(tmp2);
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}
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tcg_temp_free(addr);
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}
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} else {
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/* Load/store multiple, RFE, SRS. */
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@ -7440,21 +7444,27 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
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}
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break;
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case 5: /* Data processing register constant shift. */
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if (rn == 15)
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gen_op_movl_T0_im(0);
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else
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gen_movl_T0_reg(s, rn);
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gen_movl_T1_reg(s, rm);
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if (rn == 15) {
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tmp = new_tmp();
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tcg_gen_movi_i32(tmp, 0);
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} else {
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tmp = load_reg(s, rn);
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}
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tmp2 = load_reg(s, rm);
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op = (insn >> 21) & 0xf;
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shiftop = (insn >> 4) & 3;
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shift = ((insn >> 6) & 3) | ((insn >> 10) & 0x1c);
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conds = (insn & (1 << 20)) != 0;
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logic_cc = (conds && thumb2_logic_op(op));
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gen_arm_shift_im(cpu_T[1], shiftop, shift, logic_cc);
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if (gen_thumb2_data_op(s, op, conds, 0, cpu_T[0], cpu_T[1]))
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gen_arm_shift_im(tmp2, shiftop, shift, logic_cc);
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if (gen_thumb2_data_op(s, op, conds, 0, tmp, tmp2))
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goto illegal_op;
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if (rd != 15)
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gen_movl_reg_T0(s, rd);
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dead_tmp(tmp2);
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if (rd != 15) {
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store_reg(s, rd, tmp);
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} else {
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dead_tmp(tmp);
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}
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break;
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case 13: /* Misc data processing. */
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op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
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@ -7741,8 +7751,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
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if (insn & (1 << 14)) {
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/* Branch and link. */
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gen_op_movl_T1_im(s->pc | 1);
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gen_movl_reg_T1(s, 14);
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tcg_gen_movi_i32(cpu_R[14], s->pc | 1);
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}
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offset += s->pc;
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@ -8005,19 +8014,25 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1)
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shifter_out = 1;
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break;
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}
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gen_op_movl_T1_im(imm);
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tmp2 = new_tmp();
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tcg_gen_movi_i32(tmp2, imm);
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rn = (insn >> 16) & 0xf;
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if (rn == 15)
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gen_op_movl_T0_im(0);
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else
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gen_movl_T0_reg(s, rn);
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if (rn == 15) {
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tmp = new_tmp();
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tcg_gen_movi_i32(tmp, 0);
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} else {
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tmp = load_reg(s, rn);
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}
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op = (insn >> 21) & 0xf;
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if (gen_thumb2_data_op(s, op, (insn & (1 << 20)) != 0,
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shifter_out, cpu_T[0], cpu_T[1]))
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shifter_out, tmp, tmp2))
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goto illegal_op;
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dead_tmp(tmp2);
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rd = (insn >> 8) & 0xf;
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if (rd != 15) {
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gen_movl_reg_T0(s, rd);
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store_reg(s, rd, tmp);
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} else {
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dead_tmp(tmp);
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}
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}
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}
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