mirror of https://gitee.com/openkylin/qemu.git
target/arm: Implement PMOVSSET
Add an array for PMOVSSET so we only define it for v7ve+ platforms Signed-off-by: Aaron Lindsay <alindsay@codeaurora.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20181211151945.29137-7-aaron@os.amperecomputing.com Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -1342,6 +1342,13 @@ static void pmovsr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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env->cp15.c9_pmovsr &= ~value;
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}
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static void pmovsset_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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value &= pmu_counter_mask(env);
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env->cp15.c9_pmovsr |= value;
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}
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static void pmxevtyper_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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@ -1718,6 +1725,24 @@ static const ARMCPRegInfo v7mp_cp_reginfo[] = {
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REGINFO_SENTINEL
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};
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static const ARMCPRegInfo pmovsset_cp_reginfo[] = {
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/* PMOVSSET is not implemented in v7 before v7ve */
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{ .name = "PMOVSSET", .cp = 15, .opc1 = 0, .crn = 9, .crm = 14, .opc2 = 3,
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.access = PL0_RW, .accessfn = pmreg_access,
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.type = ARM_CP_ALIAS,
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.fieldoffset = offsetoflow32(CPUARMState, cp15.c9_pmovsr),
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.writefn = pmovsset_write,
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.raw_writefn = raw_write },
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{ .name = "PMOVSSET_EL0", .state = ARM_CP_STATE_AA64,
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.opc0 = 3, .opc1 = 3, .crn = 9, .crm = 14, .opc2 = 3,
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.access = PL0_RW, .accessfn = pmreg_access,
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.type = ARM_CP_ALIAS,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmovsr),
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.writefn = pmovsset_write,
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.raw_writefn = raw_write },
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REGINFO_SENTINEL
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};
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static void teecr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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uint64_t value)
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{
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@ -5360,6 +5385,9 @@ void register_cp_regs_for_features(ARMCPU *cpu)
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!arm_feature(env, ARM_FEATURE_PMSA)) {
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define_arm_cp_regs(cpu, v7mp_cp_reginfo);
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}
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if (arm_feature(env, ARM_FEATURE_V7VE)) {
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define_arm_cp_regs(cpu, pmovsset_cp_reginfo);
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}
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if (arm_feature(env, ARM_FEATURE_V7)) {
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/* v7 performance monitor control register: same implementor
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* field as main ID register, and we implement only the cycle
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