mirror of https://gitee.com/openkylin/qemu.git
target/arm: Cache the Tagged bit for a page in MemTxAttrs
This "bit" is a particular value of the page's MemAttr. Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Message-id: 20200626033144.790098-43-richard.henderson@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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@ -11834,9 +11834,19 @@ static uint8_t combine_cacheattr_nibble(uint8_t s1, uint8_t s2)
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*/
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*/
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static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2)
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static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2)
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{
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{
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uint8_t s1lo = extract32(s1.attrs, 0, 4), s2lo = extract32(s2.attrs, 0, 4);
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uint8_t s1lo, s2lo, s1hi, s2hi;
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uint8_t s1hi = extract32(s1.attrs, 4, 4), s2hi = extract32(s2.attrs, 4, 4);
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ARMCacheAttrs ret;
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ARMCacheAttrs ret;
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bool tagged = false;
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if (s1.attrs == 0xf0) {
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tagged = true;
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s1.attrs = 0xff;
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}
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s1lo = extract32(s1.attrs, 0, 4);
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s2lo = extract32(s2.attrs, 0, 4);
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s1hi = extract32(s1.attrs, 4, 4);
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s2hi = extract32(s2.attrs, 4, 4);
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/* Combine shareability attributes (table D4-43) */
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/* Combine shareability attributes (table D4-43) */
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if (s1.shareability == 2 || s2.shareability == 2) {
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if (s1.shareability == 2 || s2.shareability == 2) {
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@ -11884,6 +11894,11 @@ static ARMCacheAttrs combine_cacheattrs(ARMCacheAttrs s1, ARMCacheAttrs s2)
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}
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}
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}
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}
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/* TODO: CombineS1S2Desc does not consider transient, only WB, RWA. */
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if (tagged && ret.attrs == 0xff) {
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ret.attrs = 0xf0;
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}
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return ret;
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return ret;
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}
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}
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@ -11963,8 +11978,11 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
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* Normal Non-Shareable,
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* Normal Non-Shareable,
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* Inner Write-Back Read-Allocate Write-Allocate,
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* Inner Write-Back Read-Allocate Write-Allocate,
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* Outer Write-Back Read-Allocate Write-Allocate.
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* Outer Write-Back Read-Allocate Write-Allocate.
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* Do not overwrite Tagged within attrs.
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*/
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*/
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cacheattrs->attrs = 0xff;
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if (cacheattrs->attrs != 0xf0) {
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cacheattrs->attrs = 0xff;
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}
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cacheattrs->shareability = 0;
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cacheattrs->shareability = 0;
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}
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}
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*cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2);
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*cacheattrs = combine_cacheattrs(*cacheattrs, cacheattrs2);
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@ -12029,6 +12047,9 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
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/* Definitely a real MMU, not an MPU */
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/* Definitely a real MMU, not an MPU */
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if (regime_translation_disabled(env, mmu_idx)) {
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if (regime_translation_disabled(env, mmu_idx)) {
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uint64_t hcr;
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uint8_t memattr;
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/*
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/*
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* MMU disabled. S1 addresses within aa64 translation regimes are
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* MMU disabled. S1 addresses within aa64 translation regimes are
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* still checked for bounds -- see AArch64.TranslateAddressS1Off.
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* still checked for bounds -- see AArch64.TranslateAddressS1Off.
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@ -12066,6 +12087,27 @@ bool get_phys_addr(CPUARMState *env, target_ulong address,
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*phys_ptr = address;
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*phys_ptr = address;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
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*page_size = TARGET_PAGE_SIZE;
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*page_size = TARGET_PAGE_SIZE;
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/* Fill in cacheattr a-la AArch64.TranslateAddressS1Off. */
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hcr = arm_hcr_el2_eff(env);
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cacheattrs->shareability = 0;
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if (hcr & HCR_DC) {
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if (hcr & HCR_DCT) {
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memattr = 0xf0; /* Tagged, Normal, WB, RWA */
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} else {
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memattr = 0xff; /* Normal, WB, RWA */
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}
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} else if (access_type == MMU_INST_FETCH) {
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if (regime_sctlr(env, mmu_idx) & SCTLR_I) {
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memattr = 0xee; /* Normal, WT, RA, NT */
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} else {
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memattr = 0x44; /* Normal, NC, No */
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}
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cacheattrs->shareability = 2; /* outer sharable */
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} else {
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memattr = 0x00; /* Device, nGnRnE */
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}
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cacheattrs->attrs = memattr;
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return 0;
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return 0;
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}
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}
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@ -188,6 +188,11 @@ bool arm_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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phys_addr &= TARGET_PAGE_MASK;
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phys_addr &= TARGET_PAGE_MASK;
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address &= TARGET_PAGE_MASK;
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address &= TARGET_PAGE_MASK;
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}
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}
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/* Notice and record tagged memory. */
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if (cpu_isar_feature(aa64_mte, cpu) && cacheattrs.attrs == 0xf0) {
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arm_tlb_mte_tagged(&attrs) = true;
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}
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tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
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tlb_set_page_with_attrs(cs, address, phys_addr, attrs,
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prot, mmu_idx, page_size);
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prot, mmu_idx, page_size);
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return true;
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return true;
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