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qemu-log: add log category for MMU info 

Running barebox on qemu-system-mips* with '-d unimp' overloads
stderr by very very many mips_cpu_handle_mmu_fault() messages:

  mips_cpu_handle_mmu_fault address=b80003fd ret 0 physical 00000000180003fd prot 3
  mips_cpu_handle_mmu_fault address=a0800884 ret 0 physical 0000000000800884 prot 3
  mips_cpu_handle_mmu_fault pc a080cd80 ad b80003fd rw 0 mmu_idx 0

So it's very difficult to find LOG_UNIMP message.

The mips_cpu_handle_mmu_fault() messages appear on enabling ANY
logging! It's not very handy.

Adding separate log category for *_cpu_handle_mmu_fault()
logging fixes the problem.

Signed-off-by: Antony Pavlov <antonynpavlov@gmail.com>
Acked-by: Alexander Graf <agraf@suse.de>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Message-id: 1418489298-1184-1-git-send-email-antonynpavlov@gmail.com
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This commit is contained in:
Antony Pavlov 2014-12-13 19:48:18 +03:00 committed by Peter Maydell
parent d86fb03469
commit 339aaf5b7f
12 changed files with 61 additions and 58 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
cputlb.c
View File

@ -270,7 +270,8 @@ void tlb_set_page(CPUState *cpu, target_ulong vaddr,
assert(sz >= TARGET_PAGE_SIZE); assert(sz >= TARGET_PAGE_SIZE);
#if defined(DEBUG_TLB) #if defined(DEBUG_TLB)
printf("tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx qemu_log_mask(CPU_LOG_MMU,
"tlb_set_page: vaddr=" TARGET_FMT_lx " paddr=0x" TARGET_FMT_plx
" prot=%x idx=%d\n", " prot=%x idx=%d\n",
vaddr, paddr, prot, mmu_idx); vaddr, paddr, prot, mmu_idx);
#endif #endif

1
include/qemu/log.h
View File

@ -40,6 +40,7 @@ static inline bool qemu_log_enabled(void)
#define CPU_LOG_RESET (1 << 9) #define CPU_LOG_RESET (1 << 9)
#define LOG_UNIMP (1 << 10) #define LOG_UNIMP (1 << 10)
#define LOG_GUEST_ERROR (1 << 11) #define LOG_GUEST_ERROR (1 << 11)
#define CPU_LOG_MMU (1 << 12)
/* Returns true if a bit is set in the current loglevel mask /* Returns true if a bit is set in the current loglevel mask
*/ */

2
qemu-log.c
View File

@ -106,6 +106,8 @@ const QEMULogItem qemu_log_items[] = {
"show trace before each executed TB (lots of logs)" }, "show trace before each executed TB (lots of logs)" },
{ CPU_LOG_TB_CPU, "cpu", { CPU_LOG_TB_CPU, "cpu",
"show CPU state before block translation" }, "show CPU state before block translation" },
{ CPU_LOG_MMU, "mmu",
"log MMU-related activities" },
{ CPU_LOG_PCALL, "pcall", { CPU_LOG_PCALL, "pcall",
"x86 only: show protected mode far calls/returns/exceptions" }, "x86 only: show protected mode far calls/returns/exceptions" },
{ CPU_LOG_RESET, "cpu_reset", { CPU_LOG_RESET, "cpu_reset",

11
target-cris/helper.c
View File

@ -84,8 +84,8 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
int r = -1; int r = -1;
target_ulong phy; target_ulong phy;
D(printf("%s addr=%" VADDR_PRIx " pc=%x rw=%x\n", qemu_log_mask(CPU_LOG_MMU, "%s addr=%" VADDR_PRIx " pc=%x rw=%x\n",
__func__, address, env->pc, rw)); __func__, address, env->pc, rw);
miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK, miss = cris_mmu_translate(&res, env, address & TARGET_PAGE_MASK,
rw, mmu_idx, 0); rw, mmu_idx, 0);
if (miss) { if (miss) {
@ -112,9 +112,10 @@ int cris_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
r = 0; r = 0;
} }
if (r > 0) { if (r > 0) {
D_LOG("%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x" qemu_log_mask(CPU_LOG_MMU,
" pc=%x\n", __func__, r, cs->interrupt_request, address, res.phy, "%s returns %d irqreq=%x addr=%" VADDR_PRIx " phy=%x vec=%x"
res.bf_vec, env->pc); " pc=%x\n", __func__, r, cs->interrupt_request, address,
res.phy, res.bf_vec, env->pc);
} }
return r; return r;
} }

15
target-i386/helper.c
View File

@ -25,8 +25,6 @@
#include "monitor/monitor.h" #include "monitor/monitor.h"
#endif #endif
//#define DEBUG_MMU
static void cpu_x86_version(CPUX86State *env, int *family, int *model) static void cpu_x86_version(CPUX86State *env, int *family, int *model)
{ {
int cpuver = env->cpuid_version; int cpuver = env->cpuid_version;
@ -388,9 +386,7 @@ void x86_cpu_set_a20(X86CPU *cpu, int a20_state)
if (a20_state != ((env->a20_mask >> 20) & 1)) { if (a20_state != ((env->a20_mask >> 20) & 1)) {
CPUState *cs = CPU(cpu); CPUState *cs = CPU(cpu);
#if defined(DEBUG_MMU) qemu_log_mask(CPU_LOG_MMU, "A20 update: a20=%d\n", a20_state);
printf("A20 update: a20=%d\n", a20_state);
#endif
/* if the cpu is currently executing code, we must unlink it and /* if the cpu is currently executing code, we must unlink it and
all the potentially executing TB */ all the potentially executing TB */
cpu_interrupt(cs, CPU_INTERRUPT_EXITTB); cpu_interrupt(cs, CPU_INTERRUPT_EXITTB);
@ -407,9 +403,7 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
X86CPU *cpu = x86_env_get_cpu(env); X86CPU *cpu = x86_env_get_cpu(env);
int pe_state; int pe_state;
#if defined(DEBUG_MMU) qemu_log_mask(CPU_LOG_MMU, "CR0 update: CR0=0x%08x\n", new_cr0);
printf("CR0 update: CR0=0x%08x\n", new_cr0);
#endif
if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) != if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
(env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) { (env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
tlb_flush(CPU(cpu), 1); tlb_flush(CPU(cpu), 1);
@ -452,9 +446,8 @@ void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
env->cr[3] = new_cr3; env->cr[3] = new_cr3;
if (env->cr[0] & CR0_PG_MASK) { if (env->cr[0] & CR0_PG_MASK) {
#if defined(DEBUG_MMU) qemu_log_mask(CPU_LOG_MMU,
printf("CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3); "CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
#endif
tlb_flush(CPU(cpu), 0); tlb_flush(CPU(cpu), 0);
} }
} }

8
target-microblaze/helper.c
View File

@ -22,7 +22,6 @@
#include "qemu/host-utils.h" #include "qemu/host-utils.h"
#define D(x) #define D(x)
#define DMMU(x)
#if defined(CONFIG_USER_ONLY) #if defined(CONFIG_USER_ONLY)
@ -75,13 +74,14 @@ int mb_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
vaddr = address & TARGET_PAGE_MASK; vaddr = address & TARGET_PAGE_MASK;
paddr = lu.paddr + vaddr - lu.vaddr; paddr = lu.paddr + vaddr - lu.vaddr;
DMMU(qemu_log("MMU map mmu=%d v=%x p=%x prot=%x\n", qemu_log_mask(CPU_LOG_MMU, "MMU map mmu=%d v=%x p=%x prot=%x\n",
mmu_idx, vaddr, paddr, lu.prot)); mmu_idx, vaddr, paddr, lu.prot);
tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE); tlb_set_page(cs, vaddr, paddr, lu.prot, mmu_idx, TARGET_PAGE_SIZE);
r = 0; r = 0;
} else { } else {
env->sregs[SR_EAR] = address; env->sregs[SR_EAR] = address;
DMMU(qemu_log("mmu=%d miss v=%x\n", mmu_idx, address)); qemu_log_mask(CPU_LOG_MMU, "mmu=%d miss v=%" VADDR_PRIx "\n",
mmu_idx, address);
switch (lu.err) { switch (lu.err) {
case ERR_PROT: case ERR_PROT:

6
target-mips/helper.c
View File

@ -341,7 +341,8 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
#if 0 #if 0
log_cpu_state(cs, 0); log_cpu_state(cs, 0);
#endif #endif
qemu_log("%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n", qemu_log_mask(CPU_LOG_MMU,
"%s pc " TARGET_FMT_lx " ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
__func__, env->active_tc.PC, address, rw, mmu_idx); __func__, env->active_tc.PC, address, rw, mmu_idx);
/* data access */ /* data access */
@ -351,7 +352,8 @@ int mips_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
access_type = ACCESS_INT; access_type = ACCESS_INT;
ret = get_physical_address(env, &physical, &prot, ret = get_physical_address(env, &physical, &prot,
address, rw, access_type); address, rw, access_type);
qemu_log("%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx qemu_log_mask(CPU_LOG_MMU,
"%s address=%" VADDR_PRIx " ret %d physical " TARGET_FMT_plx
" prot %d\n", " prot %d\n",
__func__, address, ret, physical, prot); __func__, address, ret, physical, prot);
if (ret == TLBRET_MATCH) { if (ret == TLBRET_MATCH) {

18
target-ppc/mmu-hash32.c
View File

@ -28,10 +28,8 @@
//#define DEBUG_BAT //#define DEBUG_BAT
#ifdef DEBUG_MMU #ifdef DEBUG_MMU
# define LOG_MMU(...) qemu_log(__VA_ARGS__)
# define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0) # define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0)
#else #else
# define LOG_MMU(...) do { } while (0)
# define LOG_MMU_STATE(cpu) do { } while (0) # define LOG_MMU_STATE(cpu) do { } while (0)
#endif #endif
@ -225,7 +223,7 @@ static int ppc_hash32_direct_store(CPUPPCState *env, target_ulong sr,
CPUState *cs = CPU(ppc_env_get_cpu(env)); CPUState *cs = CPU(ppc_env_get_cpu(env));
int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS)); int key = !!(msr_pr ? (sr & SR32_KP) : (sr & SR32_KS));
LOG_MMU("direct store...\n"); qemu_log_mask(CPU_LOG_MMU, "direct store...\n");
if ((sr & 0x1FF00000) >> 20 == 0x07f) { if ((sr & 0x1FF00000) >> 20 == 0x07f) {
/* Memory-forced I/O controller interface access */ /* Memory-forced I/O controller interface access */
@ -348,12 +346,13 @@ static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
ptem = (vsid << 7) | (pgidx >> 10); ptem = (vsid << 7) | (pgidx >> 10);
/* Page address translation */ /* Page address translation */
LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx
" htab_mask " TARGET_FMT_plx
" hash " TARGET_FMT_plx "\n", " hash " TARGET_FMT_plx "\n",
env->htab_base, env->htab_mask, hash); env->htab_base, env->htab_mask, hash);
/* Primary PTEG lookup */ /* Primary PTEG lookup */
LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx qemu_log_mask(CPU_LOG_MMU, "0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
" vsid=%" PRIx32 " ptem=%" PRIx32 " vsid=%" PRIx32 " ptem=%" PRIx32
" hash=" TARGET_FMT_plx "\n", " hash=" TARGET_FMT_plx "\n",
env->htab_base, env->htab_mask, vsid, ptem, hash); env->htab_base, env->htab_mask, vsid, ptem, hash);
@ -361,7 +360,7 @@ static hwaddr ppc_hash32_htab_lookup(CPUPPCState *env,
pte_offset = ppc_hash32_pteg_search(env, pteg_off, 0, ptem, pte); pte_offset = ppc_hash32_pteg_search(env, pteg_off, 0, ptem, pte);
if (pte_offset == -1) { if (pte_offset == -1) {
/* Secondary PTEG lookup */ /* Secondary PTEG lookup */
LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx qemu_log_mask(CPU_LOG_MMU, "1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
" vsid=%" PRIx32 " api=%" PRIx32 " vsid=%" PRIx32 " api=%" PRIx32
" hash=" TARGET_FMT_plx "\n", env->htab_base, " hash=" TARGET_FMT_plx "\n", env->htab_base,
env->htab_mask, vsid, ptem, ~hash); env->htab_mask, vsid, ptem, ~hash);
@ -476,7 +475,8 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
return 1; return 1;
} }
LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset); qemu_log_mask(CPU_LOG_MMU,
"found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
/* 7. Check access permissions */ /* 7. Check access permissions */
@ -484,7 +484,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
if (need_prot[rwx] & ~prot) { if (need_prot[rwx] & ~prot) {
/* Access right violation */ /* Access right violation */
LOG_MMU("PTE access rejected\n"); qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
if (rwx == 2) { if (rwx == 2) {
cs->exception_index = POWERPC_EXCP_ISI; cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x08000000; env->error_code = 0x08000000;
@ -501,7 +501,7 @@ int ppc_hash32_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr, int rwx,
return 1; return 1;
} }
LOG_MMU("PTE access granted !\n"); qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
/* 8. Update PTE referenced and changed bits if necessary */ /* 8. Update PTE referenced and changed bits if necessary */

18
target-ppc/mmu-hash64.c
View File

@ -27,10 +27,8 @@
//#define DEBUG_SLB //#define DEBUG_SLB
#ifdef DEBUG_MMU #ifdef DEBUG_MMU
# define LOG_MMU(...) qemu_log(__VA_ARGS__)
# define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0) # define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0)
#else #else
# define LOG_MMU(...) do { } while (0)
# define LOG_MMU_STATE(cpu) do { } while (0) # define LOG_MMU_STATE(cpu) do { } while (0)
#endif #endif
@ -420,12 +418,14 @@ static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env,
ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN); ptem = (slb->vsid & SLB_VSID_PTEM) | ((epn >> 16) & HPTE64_V_AVPN);
/* Page address translation */ /* Page address translation */
LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx qemu_log_mask(CPU_LOG_MMU,
"htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx
" hash " TARGET_FMT_plx "\n", " hash " TARGET_FMT_plx "\n",
env->htab_base, env->htab_mask, hash); env->htab_base, env->htab_mask, hash);
/* Primary PTEG lookup */ /* Primary PTEG lookup */
LOG_MMU("0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx qemu_log_mask(CPU_LOG_MMU,
"0 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
" vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx " vsid=" TARGET_FMT_lx " ptem=" TARGET_FMT_lx
" hash=" TARGET_FMT_plx "\n", " hash=" TARGET_FMT_plx "\n",
env->htab_base, env->htab_mask, vsid, ptem, hash); env->htab_base, env->htab_mask, vsid, ptem, hash);
@ -433,7 +433,8 @@ static hwaddr ppc_hash64_htab_lookup(CPUPPCState *env,
if (pte_offset == -1) { if (pte_offset == -1) {
/* Secondary PTEG lookup */ /* Secondary PTEG lookup */
LOG_MMU("1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx qemu_log_mask(CPU_LOG_MMU,
"1 htab=" TARGET_FMT_plx "/" TARGET_FMT_plx
" vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx " vsid=" TARGET_FMT_lx " api=" TARGET_FMT_lx
" hash=" TARGET_FMT_plx "\n", env->htab_base, " hash=" TARGET_FMT_plx "\n", env->htab_base,
env->htab_mask, vsid, ptem, ~hash); env->htab_mask, vsid, ptem, ~hash);
@ -522,7 +523,8 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
} }
return 1; return 1;
} }
LOG_MMU("found PTE at offset %08" HWADDR_PRIx "\n", pte_offset); qemu_log_mask(CPU_LOG_MMU,
"found PTE at offset %08" HWADDR_PRIx "\n", pte_offset);
/* 5. Check access permissions */ /* 5. Check access permissions */
@ -532,7 +534,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
if ((need_prot[rwx] & ~prot) != 0) { if ((need_prot[rwx] & ~prot) != 0) {
/* Access right violation */ /* Access right violation */
LOG_MMU("PTE access rejected\n"); qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
if (rwx == 2) { if (rwx == 2) {
cs->exception_index = POWERPC_EXCP_ISI; cs->exception_index = POWERPC_EXCP_ISI;
env->error_code = 0x08000000; env->error_code = 0x08000000;
@ -556,7 +558,7 @@ int ppc_hash64_handle_mmu_fault(PowerPCCPU *cpu, target_ulong eaddr,
return 1; return 1;
} }
LOG_MMU("PTE access granted !\n"); qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
/* 6. Update PTE referenced and changed bits if necessary */ /* 6. Update PTE referenced and changed bits if necessary */

26
target-ppc/mmu_helper.c
View File

@ -32,10 +32,8 @@
//#define FLUSH_ALL_TLBS //#define FLUSH_ALL_TLBS
#ifdef DEBUG_MMU #ifdef DEBUG_MMU
# define LOG_MMU(...) qemu_log(__VA_ARGS__)
# define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0) # define LOG_MMU_STATE(cpu) log_cpu_state((cpu), 0)
#else #else
# define LOG_MMU(...) do { } while (0)
# define LOG_MMU_STATE(cpu) do { } while (0) # define LOG_MMU_STATE(cpu) do { } while (0)
#endif #endif
@ -176,10 +174,10 @@ static inline int ppc6xx_tlb_pte_check(mmu_ctx_t *ctx, target_ulong pte0,
ret = check_prot(ctx->prot, rw, type); ret = check_prot(ctx->prot, rw, type);
if (ret == 0) { if (ret == 0) {
/* Access granted */ /* Access granted */
LOG_MMU("PTE access granted !\n"); qemu_log_mask(CPU_LOG_MMU, "PTE access granted !\n");
} else { } else {
/* Access right violation */ /* Access right violation */
LOG_MMU("PTE access rejected\n"); qemu_log_mask(CPU_LOG_MMU, "PTE access rejected\n");
} }
} }
} }
@ -480,8 +478,9 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
ctx->nx = sr & 0x10000000 ? 1 : 0; ctx->nx = sr & 0x10000000 ? 1 : 0;
vsid = sr & 0x00FFFFFF; vsid = sr & 0x00FFFFFF;
target_page_bits = TARGET_PAGE_BITS; target_page_bits = TARGET_PAGE_BITS;
LOG_MMU("Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx " nip=" qemu_log_mask(CPU_LOG_MMU,
TARGET_FMT_lx " lr=" TARGET_FMT_lx "Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx
" nip=" TARGET_FMT_lx " lr=" TARGET_FMT_lx
" ir=%d dr=%d pr=%d %d t=%d\n", " ir=%d dr=%d pr=%d %d t=%d\n",
eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir, eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
(int)msr_dr, pr != 0 ? 1 : 0, rw, type); (int)msr_dr, pr != 0 ? 1 : 0, rw, type);
@ -489,14 +488,16 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
hash = vsid ^ pgidx; hash = vsid ^ pgidx;
ctx->ptem = (vsid << 7) | (pgidx >> 10); ctx->ptem = (vsid << 7) | (pgidx >> 10);
LOG_MMU("pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n", qemu_log_mask(CPU_LOG_MMU,
"pte segment: key=%d ds %d nx %d vsid " TARGET_FMT_lx "\n",
ctx->key, ds, ctx->nx, vsid); ctx->key, ds, ctx->nx, vsid);
ret = -1; ret = -1;
if (!ds) { if (!ds) {
/* Check if instruction fetch is allowed, if needed */ /* Check if instruction fetch is allowed, if needed */
if (type != ACCESS_CODE || ctx->nx == 0) { if (type != ACCESS_CODE || ctx->nx == 0) {
/* Page address translation */ /* Page address translation */
LOG_MMU("htab_base " TARGET_FMT_plx " htab_mask " TARGET_FMT_plx qemu_log_mask(CPU_LOG_MMU, "htab_base " TARGET_FMT_plx
" htab_mask " TARGET_FMT_plx
" hash " TARGET_FMT_plx "\n", " hash " TARGET_FMT_plx "\n",
env->htab_base, env->htab_mask, hash); env->htab_base, env->htab_mask, hash);
ctx->hash[0] = hash; ctx->hash[0] = hash;
@ -527,13 +528,13 @@ static inline int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
} }
#endif #endif
} else { } else {
LOG_MMU("No access allowed\n"); qemu_log_mask(CPU_LOG_MMU, "No access allowed\n");
ret = -3; ret = -3;
} }
} else { } else {
target_ulong sr; target_ulong sr;
LOG_MMU("direct store...\n"); qemu_log_mask(CPU_LOG_MMU, "direct store...\n");
/* Direct-store segment : absolutely *BUGGY* for now */ /* Direct-store segment : absolutely *BUGGY* for now */
/* Direct-store implies a 32-bit MMU. /* Direct-store implies a 32-bit MMU.
@ -2037,7 +2038,7 @@ void ppc_store_sdr1(CPUPPCState *env, target_ulong value)
{ {
PowerPCCPU *cpu = ppc_env_get_cpu(env); PowerPCCPU *cpu = ppc_env_get_cpu(env);
LOG_MMU("%s: " TARGET_FMT_lx "\n", __func__, value); qemu_log_mask(CPU_LOG_MMU, "%s: " TARGET_FMT_lx "\n", __func__, value);
assert(!env->external_htab); assert(!env->external_htab);
if (env->spr[SPR_SDR1] != value) { if (env->spr[SPR_SDR1] != value) {
env->spr[SPR_SDR1] = value; env->spr[SPR_SDR1] = value;
@ -2079,7 +2080,8 @@ void helper_store_sr(CPUPPCState *env, target_ulong srnum, target_ulong value)
{ {
PowerPCCPU *cpu = ppc_env_get_cpu(env); PowerPCCPU *cpu = ppc_env_get_cpu(env);
LOG_MMU("%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__, qemu_log_mask(CPU_LOG_MMU,
"%s: reg=%d " TARGET_FMT_lx " " TARGET_FMT_lx "\n", __func__,
(int)srnum, value, env->sr[srnum]); (int)srnum, value, env->sr[srnum]);
#if defined(TARGET_PPC64) #if defined(TARGET_PPC64)
if (env->mmu_model & POWERPC_MMU_64) { if (env->mmu_model & POWERPC_MMU_64) {

4
target-s390x/helper.c
View File

@ -461,8 +461,8 @@ int s390_cpu_handle_mmu_fault(CPUState *cs, vaddr orig_vaddr,
return 1; return 1;
} }
DPRINTF("%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n", __func__, qemu_log_mask(CPU_LOG_MMU, "%s: set tlb %" PRIx64 " -> %" PRIx64 " (%x)\n",
(uint64_t)vaddr, (uint64_t)raddr, prot); __func__, (uint64_t)vaddr, (uint64_t)raddr, prot);
tlb_set_page(cs, orig_vaddr, raddr, prot, tlb_set_page(cs, orig_vaddr, raddr, prot,
mmu_idx, TARGET_PAGE_SIZE); mmu_idx, TARGET_PAGE_SIZE);

7
target-sparc/mmu_helper.c
View File

@ -213,10 +213,9 @@ int sparc_cpu_handle_mmu_fault(CPUState *cs, vaddr address, int rw,
address, rw, mmu_idx, &page_size); address, rw, mmu_idx, &page_size);
vaddr = address; vaddr = address;
if (error_code == 0) { if (error_code == 0) {
#ifdef DEBUG_MMU qemu_log_mask(CPU_LOG_MMU,
printf("Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr " "Translate at %" VADDR_PRIx " -> " TARGET_FMT_plx ", vaddr "
TARGET_FMT_lx "\n", address, paddr, vaddr); TARGET_FMT_lx "\n", address, paddr, vaddr);
#endif
tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size); tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
return 0; return 0;
} }