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target-mips: Fix incorrect code and test for INSV 

Content of register rs should be shifted for pos before applying a mask.
This change contains both fix for the instruction and to the existing test.

Signed-off-by: Petar Jovanovic <petarj@mips.com>
Reviewed-by: Eric Johnson <ericj@mips.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
This commit is contained in:
Petar Jovanovic 2012-11-26 16:13:21 +01:00 committed by Aurelien Jarno
parent 80625b97b5
commit 34f5606ee1
2 changed files with 2 additions and 2 deletions
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2
target-mips/dsp_helper.c
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@ -3152,7 +3152,7 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong rs, \
\
filter = ((int32_t)0x01 << size) - 1; \
filter = filter << pos; \
temprs = rs & filter; \
temprs = (rs << pos) & filter; \
temprt = rt & ~filter; \
temp = temprs | temprt; \
\

2
tests/tcg/mips/mips32-dsp/insv.c
View File

@ -10,7 +10,7 @@ int main()
dsp = 0x305;
rt = 0x12345678;
rs = 0x87654321;
result = 0x12345338;
result = 0x12345438;
__asm
("wrdsp %2, 0x03\n\t"
"insv %0, %1\n\t"