mirror of https://gitee.com/openkylin/qemu.git
target-arm: emulate LL/SC using cmpxchg helpers
Emulating LL/SC with cmpxchg is not correct, since it can suffer from the ABA problem. Portable parallel code, however, is written assuming only cmpxchg--and not LL/SC--is available. This means that in practice emulating LL/SC with cmpxchg is a viable alternative. The appended emulates LL/SC pairs in ARM with cmpxchg helpers. This works in both user and system mode. In usermode, it avoids pausing all other CPUs to perform the LL/SC pair. The subsequent performance and scalability improvement is significant, as the plots below show. They plot the throughput of atomic_add-bench compiled for ARM and executed on a 64-core x86 machine. Hi-res plots: http://imgur.com/a/aNQpB atomic_add-bench: 1000000 ops/thread, [0,1] range 9 ++---------+----------+----------+----------+----------+----------+---++ +cmpxchg +-E--+ + + + + + | 8 +Emaster +-H--+ ++ | | | 7 ++E ++ | | | 6 ++++ ++ | | | 5 ++ | ++ 4 ++ | ++ | | | 3 ++ | ++ | | | 2 ++ | ++ |H++E+--- +++ ---+E+------+E+------+E| 1 +++ +E+-----+E+------+E+------+E+------+E+-- +++ +++ ++ ++H+ + +++ + +++ ++++ + + + | 0 ++--H----H-+-----H----+----------+----------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads atomic_add-bench: 1000000 ops/thread, [0,2] range 16 ++---------+----------+---------+----------+----------+----------+---++ +cmpxchg +-E--+ + + + + + | 14 ++master +-H--+ ++ | | | 12 ++| ++ | E | 10 ++| ++ | | | 8 ++++ ++ |E+| | | | | 6 ++ | ++ | | | 4 ++ | ++ | +E+--- +++ +++ +++ ---+E+------+E| 2 +H+ +E+------E-------+E+-----+E+------+E+------+E+-- +++ + | + +++ + ++++ + + + | 0 ++H-H----H-+-----H----+---------+----------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads atomic_add-bench: 1000000 ops/thread, [0,128] range 70 ++---------+----------+---------+----------+----------+----------+---++ +cmpxchg +-E--+ + + + ++++ + | 60 ++master +-H--+ ----E------+E+-------++ | -+E+--- +++ +++ +E| | +++ ---- +++ ++| 50 ++ +++ ---+E+- ++ | -E--- | 40 ++ ---+++ ++ | +++--- | | -+E+ | 30 ++ +++---- ++ | +E+ | 20 ++ +++-- ++ | +E+ | |+E+ | 10 +E+ ++ + + + + + + + | 0 +HH-H----H-+-----H----+---------+----------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads atomic_add-bench: 1000000 ops/thread, [0,1024] range 120 ++---------+---------+----------+---------+----------+----------+---++ +cmpxchg +-E--+ + + + + + | | master +-H--+ ++| 100 ++ ----E+ | +++ ---+E+--- ++| | --E--- +++ | 80 ++ ---- +++ ++ | ---+E+- | 60 ++ -+E+-- ++ | +++ ---- +++ | | -+E+- | 40 ++ +++---- ++ | +++ ---+E+ | | -+E+--- | 20 ++ +E+ ++ |+E+++ | +E+ + + + + + + | 0 +HH-H---H--+-----H---+----------+---------+----------+----------+---++ 0 10 20 30 40 50 60 Number of threads [rth: Enforce alignment for ldrexd.] Reviewed-by: Alex Bennée <alex.bennee@linaro.org> Signed-off-by: Emilio G. Cota <cota@braap.org> Message-Id: <1467054136-10430-23-git-send-email-cota@braap.org> Signed-off-by: Richard Henderson <rth@twiddle.net>
This commit is contained in:
Emilio G. Cota
Richard Henderson
parent
7f5616f538
commit
354161b37c
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@ -1026,9 +1026,6 @@ DO_GEN_LD(8u, MO_UB)
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DO_GEN_LD(16s, MO_SW)
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DO_GEN_LD(16u, MO_UW)
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DO_GEN_LD(32u, MO_UL)
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/* 'a' variants include an alignment check */
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DO_GEN_LD(16ua, MO_UW | MO_ALIGN)
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DO_GEN_LD(32ua, MO_UL | MO_ALIGN)
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DO_GEN_ST(8, MO_UB)
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DO_GEN_ST(16, MO_UW)
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DO_GEN_ST(32, MO_UL)
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@ -7720,45 +7717,30 @@ static void gen_logicq_cc(TCGv_i32 lo, TCGv_i32 hi)
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/* Load/Store exclusive instructions are implemented by remembering
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the value/address loaded, and seeing if these are the same
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when the store is performed. This should be sufficient to implement
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when the store is performed. This should be sufficient to implement
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the architecturally mandated semantics, and avoids having to monitor
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regular stores.
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In system emulation mode only one CPU will be running at once, so
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this sequence is effectively atomic. In user emulation mode we
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throw an exception and handle the atomic operation elsewhere. */
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regular stores. The compare vs the remembered value is done during
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the cmpxchg operation, but we must compare the addresses manually. */
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static void gen_load_exclusive(DisasContext *s, int rt, int rt2,
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TCGv_i32 addr, int size)
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{
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TCGv_i32 tmp = tcg_temp_new_i32();
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TCGMemOp opc = size | MO_ALIGN | s->be_data;
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s->is_ldex = true;
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switch (size) {
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case 0:
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gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
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break;
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case 1:
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gen_aa32_ld16ua(s, tmp, addr, get_mem_index(s));
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break;
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case 2:
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case 3:
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gen_aa32_ld32ua(s, tmp, addr, get_mem_index(s));
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break;
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default:
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abort();
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}
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if (size == 3) {
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TCGv_i32 tmp2 = tcg_temp_new_i32();
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TCGv_i32 tmp3 = tcg_temp_new_i32();
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TCGv_i64 t64 = tcg_temp_new_i64();
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tcg_gen_addi_i32(tmp2, addr, 4);
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gen_aa32_ld32u(s, tmp3, tmp2, get_mem_index(s));
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tcg_temp_free_i32(tmp2);
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tcg_gen_concat_i32_i64(cpu_exclusive_val, tmp, tmp3);
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store_reg(s, rt2, tmp3);
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gen_aa32_ld_i64(s, t64, addr, get_mem_index(s), opc);
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tcg_gen_mov_i64(cpu_exclusive_val, t64);
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tcg_gen_extr_i64_i32(tmp, tmp2, t64);
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tcg_temp_free_i64(t64);
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store_reg(s, rt2, tmp2);
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} else {
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gen_aa32_ld_i32(s, tmp, addr, get_mem_index(s), opc);
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tcg_gen_extu_i32_i64(cpu_exclusive_val, tmp);
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}
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@ -7771,23 +7753,15 @@ static void gen_clrex(DisasContext *s)
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tcg_gen_movi_i64(cpu_exclusive_addr, -1);
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}
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#ifdef CONFIG_USER_ONLY
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static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
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TCGv_i32 addr, int size)
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{
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tcg_gen_extu_i32_i64(cpu_exclusive_test, addr);
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tcg_gen_movi_i32(cpu_exclusive_info,
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size | (rd << 4) | (rt << 8) | (rt2 << 12));
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gen_exception_internal_insn(s, 4, EXCP_STREX);
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}
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#else
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static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
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TCGv_i32 addr, int size)
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{
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TCGv_i32 tmp;
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TCGv_i64 val64, extaddr;
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TCGv_i32 t0, t1, t2;
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TCGv_i64 extaddr;
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TCGv taddr;
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TCGLabel *done_label;
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TCGLabel *fail_label;
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TCGMemOp opc = size | MO_ALIGN | s->be_data;
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/* if (env->exclusive_addr == addr && env->exclusive_val == [addr]) {
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[addr] = {Rt};
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@ -7802,69 +7776,45 @@ static void gen_store_exclusive(DisasContext *s, int rd, int rt, int rt2,
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tcg_gen_brcond_i64(TCG_COND_NE, extaddr, cpu_exclusive_addr, fail_label);
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tcg_temp_free_i64(extaddr);
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tmp = tcg_temp_new_i32();
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switch (size) {
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case 0:
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gen_aa32_ld8u(s, tmp, addr, get_mem_index(s));
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break;
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case 1:
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gen_aa32_ld16u(s, tmp, addr, get_mem_index(s));
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break;
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case 2:
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case 3:
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gen_aa32_ld32u(s, tmp, addr, get_mem_index(s));
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break;
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default:
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abort();
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}
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val64 = tcg_temp_new_i64();
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taddr = gen_aa32_addr(s, addr, opc);
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t0 = tcg_temp_new_i32();
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t1 = load_reg(s, rt);
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if (size == 3) {
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TCGv_i32 tmp2 = tcg_temp_new_i32();
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TCGv_i32 tmp3 = tcg_temp_new_i32();
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tcg_gen_addi_i32(tmp2, addr, 4);
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gen_aa32_ld32u(s, tmp3, tmp2, get_mem_index(s));
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tcg_temp_free_i32(tmp2);
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tcg_gen_concat_i32_i64(val64, tmp, tmp3);
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tcg_temp_free_i32(tmp3);
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TCGv_i64 o64 = tcg_temp_new_i64();
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TCGv_i64 n64 = tcg_temp_new_i64();
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t2 = load_reg(s, rt2);
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tcg_gen_concat_i32_i64(n64, t1, t2);
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tcg_temp_free_i32(t2);
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gen_aa32_frob64(s, n64);
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tcg_gen_atomic_cmpxchg_i64(o64, taddr, cpu_exclusive_val, n64,
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get_mem_index(s), opc);
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tcg_temp_free_i64(n64);
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gen_aa32_frob64(s, o64);
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tcg_gen_setcond_i64(TCG_COND_NE, o64, o64, cpu_exclusive_val);
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tcg_gen_extrl_i64_i32(t0, o64);
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tcg_temp_free_i64(o64);
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} else {
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tcg_gen_extu_i32_i64(val64, tmp);
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t2 = tcg_temp_new_i32();
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tcg_gen_extrl_i64_i32(t2, cpu_exclusive_val);
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tcg_gen_atomic_cmpxchg_i32(t0, taddr, t2, t1, get_mem_index(s), opc);
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tcg_gen_setcond_i32(TCG_COND_NE, t0, t0, t2);
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tcg_temp_free_i32(t2);
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}
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tcg_temp_free_i32(tmp);
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tcg_gen_brcond_i64(TCG_COND_NE, val64, cpu_exclusive_val, fail_label);
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tcg_temp_free_i64(val64);
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tmp = load_reg(s, rt);
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switch (size) {
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case 0:
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gen_aa32_st8(s, tmp, addr, get_mem_index(s));
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break;
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case 1:
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gen_aa32_st16(s, tmp, addr, get_mem_index(s));
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break;
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case 2:
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case 3:
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gen_aa32_st32(s, tmp, addr, get_mem_index(s));
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break;
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default:
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abort();
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}
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tcg_temp_free_i32(tmp);
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if (size == 3) {
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tcg_gen_addi_i32(addr, addr, 4);
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tmp = load_reg(s, rt2);
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gen_aa32_st32(s, tmp, addr, get_mem_index(s));
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tcg_temp_free_i32(tmp);
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}
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tcg_gen_movi_i32(cpu_R[rd], 0);
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tcg_temp_free_i32(t1);
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tcg_temp_free(taddr);
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tcg_gen_mov_i32(cpu_R[rd], t0);
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tcg_temp_free_i32(t0);
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tcg_gen_br(done_label);
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gen_set_label(fail_label);
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tcg_gen_movi_i32(cpu_R[rd], 1);
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gen_set_label(done_label);
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tcg_gen_movi_i64(cpu_exclusive_addr, -1);
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}
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#endif
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/* gen_srs:
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* @env: CPUARMState
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