openkylin
/
qemu
mirror of https://gitee.com/openkylin/qemu.git
9
0
Fork 0
Code Issues Projects Releases Wiki Activity

hw/net/xilinx_axienet: Rename StreamSlave as StreamSink 

In order to use inclusive terminology, rename 'slave stream'
as 'sink stream'.

Signed-off-by: Philippe Mathieu-Daudé <philmd@redhat.com>
Acked-by: Paolo Bonzini <pbonzini@redhat.com>
Reviewed-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com>
Message-Id: <20200910070131.435543-5-philmd@redhat.com>
Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
This commit is contained in:
Philippe Mathieu-Daudé 2020-09-10 09:01:29 +02:00 committed by Paolo Bonzini
parent 484f86de7e
commit 357088b1ed
1 changed files with 12 additions and 12 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

24
hw/net/xilinx_axienet.c
View File

@ -45,11 +45,11 @@
OBJECT_DECLARE_SIMPLE_TYPE(XilinxAXIEnet, XILINX_AXI_ENET) OBJECT_DECLARE_SIMPLE_TYPE(XilinxAXIEnet, XILINX_AXI_ENET)
typedef struct XilinxAXIEnetStreamSlave XilinxAXIEnetStreamSlave; typedef struct XilinxAXIEnetStreamSink XilinxAXIEnetStreamSink;
DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSlave, XILINX_AXI_ENET_DATA_STREAM, DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSink, XILINX_AXI_ENET_DATA_STREAM,
TYPE_XILINX_AXI_ENET_DATA_STREAM) TYPE_XILINX_AXI_ENET_DATA_STREAM)
DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSlave, XILINX_AXI_ENET_CONTROL_STREAM, DECLARE_INSTANCE_CHECKER(XilinxAXIEnetStreamSink, XILINX_AXI_ENET_CONTROL_STREAM,
TYPE_XILINX_AXI_ENET_CONTROL_STREAM) TYPE_XILINX_AXI_ENET_CONTROL_STREAM)
/* Advertisement control register. */ /* Advertisement control register. */
@ -310,7 +310,7 @@ struct TEMAC {
}; };
struct XilinxAXIEnetStreamSlave { struct XilinxAXIEnetStreamSink {
Object parent; Object parent;
struct XilinxAXIEnet *enet; struct XilinxAXIEnet *enet;
@ -322,8 +322,8 @@ struct XilinxAXIEnet {
qemu_irq irq; qemu_irq irq;
StreamSink *tx_data_dev; StreamSink *tx_data_dev;
StreamSink *tx_control_dev; StreamSink *tx_control_dev;
XilinxAXIEnetStreamSlave rx_data_dev; XilinxAXIEnetStreamSink rx_data_dev;
XilinxAXIEnetStreamSlave rx_control_dev; XilinxAXIEnetStreamSink rx_control_dev;
NICState *nic; NICState *nic;
NICConf conf; NICConf conf;
@ -856,7 +856,7 @@ xilinx_axienet_control_stream_push(StreamSink *obj, uint8_t *buf, size_t len,
bool eop) bool eop)
{ {
int i; int i;
XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj); XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(obj);
XilinxAXIEnet *s = cs->enet; XilinxAXIEnet *s = cs->enet;
assert(eop); assert(eop);
@ -877,7 +877,7 @@ static size_t
xilinx_axienet_data_stream_push(StreamSink *obj, uint8_t *buf, size_t size, xilinx_axienet_data_stream_push(StreamSink *obj, uint8_t *buf, size_t size,
bool eop) bool eop)
{ {
XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(obj); XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(obj);
XilinxAXIEnet *s = ds->enet; XilinxAXIEnet *s = ds->enet;
/* TX enable ? */ /* TX enable ? */
@ -951,8 +951,8 @@ static NetClientInfo net_xilinx_enet_info = {
static void xilinx_enet_realize(DeviceState *dev, Error **errp) static void xilinx_enet_realize(DeviceState *dev, Error **errp)
{ {
XilinxAXIEnet *s = XILINX_AXI_ENET(dev); XilinxAXIEnet *s = XILINX_AXI_ENET(dev);
XilinxAXIEnetStreamSlave *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev); XilinxAXIEnetStreamSink *ds = XILINX_AXI_ENET_DATA_STREAM(&s->rx_data_dev);
XilinxAXIEnetStreamSlave *cs = XILINX_AXI_ENET_CONTROL_STREAM( XilinxAXIEnetStreamSink *cs = XILINX_AXI_ENET_CONTROL_STREAM(
&s->rx_control_dev); &s->rx_control_dev);
object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet", object_property_add_link(OBJECT(ds), "enet", "xlnx.axi-ethernet",
@ -1043,7 +1043,7 @@ static const TypeInfo xilinx_enet_info = {
static const TypeInfo xilinx_enet_data_stream_info = { static const TypeInfo xilinx_enet_data_stream_info = {
.name = TYPE_XILINX_AXI_ENET_DATA_STREAM, .name = TYPE_XILINX_AXI_ENET_DATA_STREAM,
.parent = TYPE_OBJECT, .parent = TYPE_OBJECT,
.instance_size = sizeof(XilinxAXIEnetStreamSlave), .instance_size = sizeof(XilinxAXIEnetStreamSink),
.class_init = xilinx_enet_data_stream_class_init, .class_init = xilinx_enet_data_stream_class_init,
.interfaces = (InterfaceInfo[]) { .interfaces = (InterfaceInfo[]) {
{ TYPE_STREAM_SINK }, { TYPE_STREAM_SINK },
@ -1054,7 +1054,7 @@ static const TypeInfo xilinx_enet_data_stream_info = {
static const TypeInfo xilinx_enet_control_stream_info = { static const TypeInfo xilinx_enet_control_stream_info = {
.name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM, .name = TYPE_XILINX_AXI_ENET_CONTROL_STREAM,
.parent = TYPE_OBJECT, .parent = TYPE_OBJECT,
.instance_size = sizeof(XilinxAXIEnetStreamSlave), .instance_size = sizeof(XilinxAXIEnetStreamSink),
.class_init = xilinx_enet_control_stream_class_init, .class_init = xilinx_enet_control_stream_class_init,
.interfaces = (InterfaceInfo[]) { .interfaces = (InterfaceInfo[]) {
{ TYPE_STREAM_SINK }, { TYPE_STREAM_SINK },