mirror of https://gitee.com/openkylin/qemu.git
target/riscv: Add H extension state description
In the case of supporting H extension, add H extension description to vmstate_riscv_cpu. Signed-off-by: Yifei Jiang <jiangyifei@huawei.com> Signed-off-by: Yipeng Yin <yinyipeng1@huawei.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Message-id: 20201026115530.304-5-jiangyifei@huawei.com Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
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@ -68,6 +68,52 @@ static const VMStateDescription vmstate_pmp = {
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}
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};
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static bool hyper_needed(void *opaque)
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{
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RISCVCPU *cpu = opaque;
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CPURISCVState *env = &cpu->env;
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return riscv_has_ext(env, RVH);
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}
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static const VMStateDescription vmstate_hyper = {
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.name = "cpu/hyper",
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.version_id = 1,
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.minimum_version_id = 1,
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.needed = hyper_needed,
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.fields = (VMStateField[]) {
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VMSTATE_UINTTL(env.hstatus, RISCVCPU),
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VMSTATE_UINTTL(env.hedeleg, RISCVCPU),
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VMSTATE_UINTTL(env.hideleg, RISCVCPU),
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VMSTATE_UINTTL(env.hcounteren, RISCVCPU),
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VMSTATE_UINTTL(env.htval, RISCVCPU),
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VMSTATE_UINTTL(env.htinst, RISCVCPU),
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VMSTATE_UINTTL(env.hgatp, RISCVCPU),
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VMSTATE_UINT64(env.htimedelta, RISCVCPU),
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VMSTATE_UINT64(env.vsstatus, RISCVCPU),
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VMSTATE_UINTTL(env.vstvec, RISCVCPU),
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VMSTATE_UINTTL(env.vsscratch, RISCVCPU),
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VMSTATE_UINTTL(env.vsepc, RISCVCPU),
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VMSTATE_UINTTL(env.vscause, RISCVCPU),
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VMSTATE_UINTTL(env.vstval, RISCVCPU),
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VMSTATE_UINTTL(env.vsatp, RISCVCPU),
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VMSTATE_UINTTL(env.mtval2, RISCVCPU),
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VMSTATE_UINTTL(env.mtinst, RISCVCPU),
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VMSTATE_UINTTL(env.stvec_hs, RISCVCPU),
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VMSTATE_UINTTL(env.sscratch_hs, RISCVCPU),
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VMSTATE_UINTTL(env.sepc_hs, RISCVCPU),
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VMSTATE_UINTTL(env.scause_hs, RISCVCPU),
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VMSTATE_UINTTL(env.stval_hs, RISCVCPU),
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VMSTATE_UINTTL(env.satp_hs, RISCVCPU),
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VMSTATE_UINT64(env.mstatus_hs, RISCVCPU),
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VMSTATE_END_OF_LIST()
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}
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};
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const VMStateDescription vmstate_riscv_cpu = {
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.name = "cpu",
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.version_id = 1,
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@ -119,6 +165,7 @@ const VMStateDescription vmstate_riscv_cpu = {
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},
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.subsections = (const VMStateDescription * []) {
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&vmstate_pmp,
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&vmstate_hyper,
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NULL
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}
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};
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