From 375ee58bedcda359011fe7fa99e0647f66f9ffa0 Mon Sep 17 00:00:00 2001 From: Aurelien Jarno Date: Wed, 3 Jun 2015 23:09:50 +0200 Subject: [PATCH] target-s390x: implement miscellaneous-instruction-extensions facility RISBGN is the same as RISBG, but without setting the condition code. CLT and CLGT are the same as CLRT and CLGRT, but using memory for the second operand. Reviewed-by: Richard Henderson Signed-off-by: Aurelien Jarno Signed-off-by: Alexander Graf --- target-s390x/insn-data.def | 3 +++ target-s390x/translate.c | 1 + 2 files changed, 4 insertions(+) diff --git a/target-s390x/insn-data.def b/target-s390x/insn-data.def index 41b5f43d53..ddc6337584 100644 --- a/target-s390x/insn-data.def +++ b/target-s390x/insn-data.def @@ -230,6 +230,8 @@ /* COMPARE LOGICAL AND TRAP */ D(0xb973, CLRT, RRF_c, GIE, r1_32u, r2_32u, 0, 0, ct, 0, 1) D(0xb961, CLGRT, RRF_c, GIE, r1_o, r2_o, 0, 0, ct, 0, 1) + D(0xeb23, CLT, RSY_b, MIE, r1_32u, m2_32u, 0, 0, ct, 0, 1) + D(0xeb2b, CLGT, RSY_b, MIE, r1_o, m2_64, 0, 0, ct, 0, 1) D(0xec73, CLFIT, RIE_a, GIE, r1_32u, i2_32u, 0, 0, ct, 0, 1) D(0xec71, CLGIT, RIE_a, GIE, r1_o, i2_32u, 0, 0, ct, 0, 1) @@ -604,6 +606,7 @@ /* ROTATE THEN INSERT SELECTED BITS */ C(0xec55, RISBG, RIE_f, GIE, 0, r2, r1, 0, risbg, s64) + C(0xec59, RISBGN, RIE_f, MIE, 0, r2, r1, 0, risbg, 0) C(0xec5d, RISBHG, RIE_f, HW, 0, r2, r1, 0, risbg, 0) C(0xec51, RISBLG, RIE_f, HW, 0, r2, r1, 0, risbg, 0) /* ROTATE_THEN SELECTED BITS */ diff --git a/target-s390x/translate.c b/target-s390x/translate.c index c8ef24a08e..fbf7f91ec0 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -1119,6 +1119,7 @@ typedef enum DisasFacility { FAC_HFP_MA, /* HFP multiply-and-add/subtract */ FAC_HW, /* high-word */ FAC_IEEEE_SIM, /* IEEE exception sumilation */ + FAC_MIE, /* miscellaneous-instruction-extensions */ FAC_LOC, /* load/store on condition */ FAC_LD, /* long displacement */ FAC_PC, /* population count */