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linux-user/elfload: Introduce MIPS GET_FEATURE_REG_SET() macro 

ISA features are usually denoted in read-only bits from
CPU registers. Add the GET_FEATURE_REG_SET() macro which
checks if a CPU register has bits set.

Use the macro to check for MSA (which sets the MSAP bit of
the Config3 register when the ASE implementation is present).

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
Message-Id: <20201214003215.344522-4-f4bug@amsat.org>
Signed-off-by: Laurent Vivier <laurent@vivier.eu>
This commit is contained in:
Philippe Mathieu-Daudé 2020-12-14 01:32:12 +01:00 committed by Laurent Vivier
parent 7d9a3d96f5
commit 388765a05b
1 changed files with 5 additions and 1 deletions
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6
linux-user/elfload.c
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@ -992,17 +992,21 @@ enum {
#define GET_FEATURE_INSN(_flag, _hwcap) \ #define GET_FEATURE_INSN(_flag, _hwcap) \
do { if (cpu->env.insn_flags & (_flag)) { hwcaps |= _hwcap; } } while (0) do { if (cpu->env.insn_flags & (_flag)) { hwcaps |= _hwcap; } } while (0)
#define GET_FEATURE_REG_SET(_reg, _mask, _hwcap) \
do { if (cpu->env._reg & (_mask)) { hwcaps |= _hwcap; } } while (0)
static uint32_t get_elf_hwcap(void) static uint32_t get_elf_hwcap(void)
{ {
MIPSCPU *cpu = MIPS_CPU(thread_cpu); MIPSCPU *cpu = MIPS_CPU(thread_cpu);
uint32_t hwcaps = 0; uint32_t hwcaps = 0;
GET_FEATURE_INSN(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6); GET_FEATURE_INSN(ISA_MIPS32R6 | ISA_MIPS64R6, HWCAP_MIPS_R6);
GET_FEATURE_INSN(ASE_MSA, HWCAP_MIPS_MSA); GET_FEATURE_REG_SET(CP0_Config3, 1 << CP0C3_MSAP, HWCAP_MIPS_MSA);
return hwcaps; return hwcaps;
} }
#undef GET_FEATURE_REG_SET
#undef GET_FEATURE_INSN #undef GET_FEATURE_INSN
#endif /* TARGET_MIPS */ #endif /* TARGET_MIPS */