From 3aa22b4b53d4a8f5ae6b073c7c267b6ec9aabf63 Mon Sep 17 00:00:00 2001
From: pbrook <pbrook@c046a42c-6fe2-441c-8c8c-71466251a162>
Date: Tue, 7 Feb 2006 03:34:35 +0000
Subject: [PATCH] Fix Thumb variable shift condition code bug.

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1748 c046a42c-6fe2-441c-8c8c-71466251a162
---
 target-arm/translate.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/target-arm/translate.c b/target-arm/translate.c
index d5cbc5ee1d..77c8957af8 100644
--- a/target-arm/translate.c
+++ b/target-arm/translate.c
@@ -1930,12 +1930,15 @@ static void disas_thumb_insn(DisasContext *s)
             break;
         case 0x2: /* lsl */
             gen_op_shll_T1_T0_cc();
+            gen_op_logic_T1_cc();
             break;
         case 0x3: /* lsr */
             gen_op_shrl_T1_T0_cc();
+            gen_op_logic_T1_cc();
             break;
         case 0x4: /* asr */
             gen_op_sarl_T1_T0_cc();
+            gen_op_logic_T1_cc();
             break;
         case 0x5: /* adc */
             gen_op_adcl_T0_T1_cc();
@@ -1945,6 +1948,7 @@ static void disas_thumb_insn(DisasContext *s)
             break;
         case 0x7: /* ror */
             gen_op_rorl_T1_T0_cc();
+            gen_op_logic_T1_cc();
             break;
         case 0x8: /* tst */
             gen_op_andl_T0_T1();